AD9542

Quad Input, Five-Output, Dual DPLL Synchronizer and Adaptive Clock Translator

Schematic Symbol

Pin Configuration (49 pins)

Pin	Name	Type
42	XOA	input
43	XOB	input
4	SDIO/SDA	bidirectional
1	SDO/M5	output
2	SCLK/SCL	input
5	CSB/M6	bidirectional
48	RESETB	input
46	REFAA	input
47	REFA	input
38	REFB	input
39	REFBB	input
3	VDDIOA	power_in
34	VDDIOB	power_in
6	VDD	power_in
9	VDD	power_in
10	VDD	power_in
13	VDD	power_in
19	VDD	power_in
20	VDD	power_in
24	VDD	power_in
27	VDD	power_in
28	VDD	power_in
31	VDD	power_in
40	VDD	power_in
41	VDD	power_in
45	VDD	power_in
11	OUT0AP	output
12	OUT0AN	output
14	OUT0BP	output
15	OUT0BN	output
17	OUT0CP	output
18	OUT0CN	output
25	OUT1AP	output
26	OUT1AN	output
22	OUT1BP	output
23	OUT1BN	output
32	M0	bidirectional
33	M1	bidirectional
35	M2	bidirectional
36	M3	bidirectional
37	M4	bidirectional
8	LF0	passive
7	LDO0	passive
29	LF1	passive
30	LDO1	passive
16	DNC	passive
21	DNC	passive
44	DNC	passive
49	EP	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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