ADCLK846

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

Schematic Symbol

Pin Configuration (25 pins)

Pin	Name	Type
3	CLK	input
2	~{CLK}	input
5	CTRL_A	input
6	CTRL_B	input
1	VREF	power_in
7	SLEEP	input
4	VS	power_in
10	VS	power_in
13	VS	power_in
16	VS	power_in
19	VS	power_in
22	VS	power_in
24	OUT0	output
23	~{OUT0}	output
21	OUT1	output
20	~{OUT1}	output
18	OUT2	output
17	~{OUT2}	output
15	OUT3	output
14	~{OUT3}	output
12	OUT4	output
11	~{OUT4}	output
9	OUT5	output
8	~{OUT5}	output
25	EP	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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