ADCLK854

1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer

Schematic Symbol

Pin Configuration (49 pins)

Pin	Name	Type
3	CLK0	input
2	~{CLK0}	input
6	CLK1	input
5	~{CLK1}	input
10	IN_SEL	input
11	CTRL_A	input
12	CTRL_B	input
13	CTRL_C	input
1	VREF	power_in
14	SLEEP	input
35	NC	power_in
36	NC	power_in
7	VS	power_in
18	VS	power_in
24	VS	power_in
30	VS	power_in
37	VS	power_in
43	VS	power_in
48	OUT0	output
47	~{OUT0}	output
46	OUT1	output
45	~{OUT1}	output
42	OUT2	output
41	~{OUT2}	output
40	OUT3	output
39	~{OUT3}	output
34	OUT4	output
33	~{OUT4}	output
32	OUT5	output
31	~{OUT5}	output
28	OUT6	output
27	~{OUT6}	output
26	OUT7	output
25	~{OUT7}	output
22	OUT8	output
21	~{OUT8}	output
20	OUT9	output
19	~{OUT9}	output
16	OUT10	output
15	~{OUT10}	output
9	OUT11	output
8	~{OUT11}	output
4	GND	power_in
17	GND	power_in
23	GND	power_in
29	GND	power_in
38	GND	power_in
44	GND	power_in
49	EP	power_in

Footprint

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