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ADCLK944
2.5V/3.3V, Four LVPECL Outputs, SiGe Clock Fanout Buffer
Schematic Symbol
Pin Configuration (17 pins)
| Pin | Name | Type |
|---|---|---|
| 3 | VREF | output |
| 2 | VT | input |
| 1 | CLK | input |
| 4 | ~{CLK} | input |
| 8 | VCC | power_in |
| 13 | VCC | power_in |
| 5 | VEE | power_in |
| 16 | VEE | power_in |
| 17 | EP | power_in |
| 15 | Q0 | output |
| 14 | ~{Q0} | output |
| 12 | Q1 | output |
| 11 | ~{Q1} | output |
| 10 | Q2 | output |
| 9 | ~{Q2} | output |
| 7 | Q3 | output |
| 6 | ~{Q3} | output |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.