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ADCLK946
3.3V, Six LVPECL Outputs, SiGe Clock Fanout Buffer
Schematic Symbol
Pin Configuration (25 pins)
| Pin | Name | Type |
|---|---|---|
| 4 | VREF | output |
| 5 | VT | input |
| 2 | CLK | input |
| 3 | ~{CLK} | input |
| 13 | VCC | power_in |
| 18 | VCC | power_in |
| 24 | VCC | power_in |
| 1 | VEE | power_in |
| 6 | VEE | power_in |
| 7 | VEE | power_in |
| 12 | VEE | power_in |
| 19 | VEE | power_in |
| 25 | EP | power_in |
| 23 | Q0 | output |
| 22 | ~{Q0} | output |
| 21 | Q1 | output |
| 20 | ~{Q1} | output |
| 17 | Q2 | output |
| 16 | ~{Q2} | output |
| 15 | Q3 | output |
| 14 | ~{Q3} | output |
| 11 | Q4 | output |
| 10 | ~{Q4} | output |
| 9 | Q5 | output |
| 8 | ~{Q5} | output |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.