ADCLK948

Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

Schematic Symbol

Pin Configuration (33 pins)

Pin	Name	Type
32	IN_SEL	input
1	CLK0	input
2	~{CLK0}	input
3	VREF0	input
4	VT0	passive
5	CLK1	input
6	~{CLK1}	input
8	VREF1	input
7	VT1	passive
9	NC	passive
10	VCC	power_in
15	VCC	power_in
16	VCC	power_in
25	VCC	power_in
26	VCC	power_in
31	VCC	power_in
33	VEE	power_in
30	Q0	output
29	~{Q0}	output
28	Q1	output
27	~{Q1}	output
24	Q2	output
23	~{Q2}	output
22	Q3	output
21	~{Q3}	output
20	Q4	output
19	~{Q4}	output
18	Q5	output
17	~{Q5}	output
14	Q6	output
13	~{Q6}	output
12	Q7	output
11	~{Q7}	output

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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