ADCLK950

Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer

Schematic Symbol

Pin Configuration (41 pins)

Pin	Name	Type
1	IN_SEL	input
2	CLK0	input
3	~{CLK0}	input
4	VREF0	input
5	VT0	passive
6	CLK1	input
7	~{CLK1}	input
9	VREF1	input
8	VT1	passive
22	NC	passive
23	NC	passive
28	NC	passive
29	NC	passive
11	VCC	power_in
20	VCC	power_in
21	VCC	power_in
30	VCC	power_in
31	VCC	power_in
40	VCC	power_in
10	VEE	power_in
41	EP	power_in
39	Q0	output
38	~{Q0}	output
37	Q1	output
36	~{Q1}	output
35	Q2	output
34	~{Q2}	output
33	Q3	output
32	~{Q3}	output
27	Q4	output
26	~{Q4}	output
25	Q5	output
24	~{Q5}	output
19	Q6	output
18	~{Q6}	output
17	Q7	output
16	~{Q7}	output
15	Q8	output
14	~{Q8}	output
13	Q9	output
12	~{Q9}	output

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

Comments

Loading comments...

Sign in to leave a comment.