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ADCLK954
Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer
Schematic Symbol
Pin Configuration (41 pins)
| Pin | Name | Type |
|---|---|---|
| 1 | IN_SEL | input |
| 2 | CLK0 | input |
| 3 | ~{CLK0} | input |
| 4 | VREF0 | input |
| 5 | VT0 | passive |
| 6 | CLK1 | input |
| 7 | ~{CLK1} | input |
| 9 | VREF1 | input |
| 8 | VT1 | passive |
| 11 | VCC | power_in |
| 20 | VCC | power_in |
| 21 | VCC | power_in |
| 30 | VCC | power_in |
| 31 | VCC | power_in |
| 40 | VCC | power_in |
| 10 | VEE | power_in |
| 41 | VEE | power_in |
| 39 | Q0 | output |
| 38 | ~{Q0} | output |
| 37 | Q1 | output |
| 36 | ~{Q1} | output |
| 35 | Q2 | output |
| 34 | ~{Q2} | output |
| 33 | Q3 | output |
| 32 | ~{Q3} | output |
| 28 | ~{Q4} | passive |
| 29 | Q4 | passive |
| 27 | Q5 | output |
| 26 | ~{Q5} | output |
| 25 | Q6 | output |
| 24 | ~{Q6} | output |
| 22 | ~{Q7} | passive |
| 23 | Q7 | passive |
| 19 | Q8 | output |
| 18 | ~{Q8} | output |
| 17 | Q9 | output |
| 16 | ~{Q9} | output |
| 15 | Q10 | output |
| 14 | ~{Q10} | output |
| 13 | Q11 | output |
| 12 | ~{Q11} | output |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.