CDC5801ADBQ

Low-Jitter Clock Multiplier & Divider with Programmable Delay & Phase Alignment

Schematic Symbol

Pin Configuration (24 pins)

Pin	Name	Type
2	REFCLK	input
24	P0	input
23	P1	input
13	P2	input
12	PWRDNB	input
11	STOPB	input
15	MULT0/DIV0	input
14	MULT1/DIV1	input
7	DLYCTRL	input
6	LEADLAG	input
1	VDDREF	power_in
3	VDDP	power_in
9	VVDPA	power_in
10	VDDDPD	power_in
16	VDDO	power_in
22	VDDO	power_in
20	CLKOUT	output
18	CLKOUTB	output
19	NC	passive
5	GND	power_in
4	GNDP	power_in
8	GNDPA	power_in
17	GNDO	power_in
21	GNDO	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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