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CDCVF2505
3.3V Clock Phase-Lock Loop Clock Driver
Schematic Symbol
Pin Configuration (8 pins)
| Pin | Name | Type |
|---|---|---|
| 1 | CLKIN | input |
| 6 | VDD | power_in |
| 4 | GND | power_in |
| 8 | CLKOUT | output |
| 3 | 1Y0 | output |
| 2 | 1Y1 | output |
| 5 | 1Y2 | output |
| 7 | 1Y3 | output |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.