CERN_GBTX ASIC_V0.1

GigaBit Transceiver ASIC (GBTX)

Schematic Symbol

Pin Configuration (400 pins)

Pin	Name	Type
C4	DINP39	input
D4	DINN39	input
G7	DINP38	input
G6	DINN38	input
N15	DINP37	input
M15	DINN37	input
D13	DINP36	input
D14	DINN36	input
E16	DINP35	input
E17	DINN35	input
R15	DINP34	input
R16	DINN34	input
T19	DINP33	input
R19	DINN33	input
U15	DINP32	input
U16	DINN32	input
R11	DINP31	input
R12	DINN31	input
R5	DINP30	input
R4	DINN30	input
J16	DINP29	input
H16	DINN29	input
L15	DINP28	input
K15	DINN28	input
L16	DINP27	input
K16	DINN27	input
M18	DINP26	input
N18	DINN26	input
M17	DINP25	input
N17	DINN25	input
P17	DINP24	input
R17	DINN24	input
T18	DINP23	input
T17	DINN23	input
T16	DINP22	input
T15	DINN22	input
D11	DINP21	input
C11	DINN21	input
E12	DINP20	input
E11	DINN20	input
F15	DINP19	input
E15	DINN19	input
D15	DINP18	input
D16	DINN18	input
F16	DINP17	input
G16	DINN17	input
F18	DINP16	input
G18	DINN16	input
B1	DINP15	input
B2	DINN15	input
D6	DINP14	input
D5	DINN14	input
B4	DINP13	input
B3	DINN13	input
F7	DINP12	input
F8	DINN12	input
F4	DINP11	input
E4	DINN11	input
D8	DINP10	input
D7	DINN10	input
E9	DINP9	input
E10	DINN9	input
D9	DINP8	input
D10	DINN8	input
V17	DINP7	input
U17	DINN7	input
U13	DINP6	input
U14	DINN6	input
U12	DINP5	input
U11	DINN5	input
T11	DINP4	input
T12	DINN4	input
R9	DINP3	input
R10	DINN3	input
U7	DINP2	input
U8	DINN2	input
T5	DINP1	input
T6	DINN1	input
U6	DINP0	input
U5	DINN0	input
H15	SLVSTESTINJECT	input
P12	SCINP	input
P13	SCINN	input
A1	DOUTP39	output
A2	DOUTN39	output
F6	DOUTP38	output
F5	DOUTN38	output
B7	DOUTP37	output
C7	DOUTN37	output
B16	DOUTP36	output
B15	DOUTN36	output
F14	DOUTP35	output
F13	DOUTN35	output
P19	DOUTP34	output
P20	DOUTN34	output
V18	DOUTP33	output
U18	DOUTN33	output
T14	DOUTP32	output
T13	DOUTN32	output
W8	DOUTP31	output
V8	DOUTN31	output
W1	DOUTP30	output
W2	DOUTN30	output
J19	DOUTP29	output
K19	DOUTN29	output
M16	DOUTP28	output
N16	DOUTN28	output
N20	DOUTP27	output
N19	DOUTN27	output
U19	DOUTP26	output
U20	DOUTN26	output
Y19	DOUTP25	output
Y20	DOUTN25	output
W15	DOUTP24	output
W16	DOUTN24	output
V13	DOUTP23	output
V14	DOUTN23	output
Y14	DOUTP22	output
Y13	DOUTN22	output
D18	DOUTP21	output
C18	DOUTN21	output
A20	DOUTP20	output
B20	DOUTN20	output
D19	DOUTP19	output
C19	DOUTN19	output
G19	DOUTP18	output
H19	DOUTN18	output
G20	DOUTP17	output
H20	DOUTN17	output
J18	DOUTP16	output
H18	DOUTN16	output
A3	DIOP15	bidirectional
A4	DION15	bidirectional
A6	DIOP14	bidirectional
A5	DION14	bidirectional
A7	DIOP13	bidirectional
A8	DION13	bidirectional
A9	DIOP12	bidirectional
A10	DION12	bidirectional
A12	DIOP11	bidirectional
A11	DION11	bidirectional
A14	DIOP10	bidirectional
A13	DION10	bidirectional
A15	DIOP9	bidirectional
A16	DION9	bidirectional
A17	DIOP8	bidirectional
A18	DION8	bidirectional
V19	DIOP7	bidirectional
W19	DION7	bidirectional
Y9	DIOP6	bidirectional
Y10	DION6	bidirectional
V7	DIOP5	bidirectional
W7	DION5	bidirectional
Y8	DIOP4	bidirectional
Y7	DION4	bidirectional
W3	DIOP3	bidirectional
V3	DION3	bidirectional
Y3	DIOP2	bidirectional
Y4	DION2	bidirectional
U4	DIOP1	bidirectional
T4	DION1	bidirectional
Y2	DIOP0	bidirectional
Y1	DION0	bidirectional
P6	SCCLKP	output
R6	SCCLKN	output
P4	SCOUTP	output
P3	SCOUTN	output
G3	DCLKP39	output
G4	DCLKN39	output
G9	DCLKP38	output
G8	DCLKN38	output
E8	DCLKP37	output
E7	DCLKN37	output
E13	DCLKP36	output
E14	DCLKN36	output
E18	DCLKP35	output
E19	DCLKN35	output
M19	DCLKP34	output
L19	DCLKN34	output
V20	DCLKP33	output
W20	DCLKN33	output
V12	DCLKP32	output
V11	DCLKN32	output
V9	DCLKP31	output
V10	DCLKN31	output
R8	DCLKP30	output
R7	DCLKN30	output
H17	DCLKP29	output
J17	DCLKN29	output
M20	DCLKP28	output
L20	DCLKN28	output
L18	DCLKP27	output
K18	DCLKN27	output
P15	DCLKP26	output
P16	DCLKN26	output
R20	DCLKP25	output
T20	DCLKN25	output
Y17	DCLKP24	output
Y18	DCLKN24	output
V16	DCLKP23	output
V15	DCLKN23	output
Y15	DCLKP22	output
Y16	DCLKN22	output
B13	DCLKP21	output
B14	DCLKN21	output
B18	DCLKP20	output
B17	DCLKN20	output
C17	DCLKP19	output
D17	DCLKN19	output
C20	DCLKP18	output
D20	DCLKN18	output
F20	DCLKP17	output
E20	DCLKN17	output
K17	DCLKP16	output
L17	DCLKN16	output
C5	DCLKP15	output
C6	DCLKN15	output
B5	DCLKP14	output
B6	DCLKN14	output
E6	DCLKP13	output
E5	DCLKN13	output
C10	DCLKP12	output
C9	DCLKN12	output
C8	DCLKP11	output
B8	DCLKN11	output
B11	DCLKP10	output
B12	DCLKN10	output
D12	DCLKP9	output
C12	DCLKN9	output
C16	DCLKP8	output
C15	DCLKN8	output
W11	DCLKP7	output
W12	DCLKN7	output
Y12	DCLKP6	output
Y11	DCLKN6	output
T10	DCLKP5	output
T9	DCLKN5	output
U9	DCLKP4	output
U10	DCLKN4	output
Y5	DCLKP3	output
Y6	DCLKN3	output
T7	DCLKP2	output
T8	DCLKN2	output
V4	DCLKP1	output
V5	DCLKN1	output
W6	DCLKP0	output
V6	DCLKN0	output
K1	REFCLKN	input
L1	REFCLKP	input
M2	XTALN	input
J2	XTALP	input
J9	REFCLKSELECT	input
H7	TESTCLOCKIN1	input
J15	TESTCLOCKIN2	input
P1	CLOCKDES7P	output
P2	CLOCKDES7N	output
M6	CLOCKDES6P	output
M7	CLOCKDES6N	output
N1	CLOCKDES5P	output
N2	CLOCKDES5N	output
M4	CLOCKDES4P	output
M5	CLOCKDES4N	output
L4	CLOCKDES3P	output
L5	CLOCKDES3N	output
K4	CLOCKDES2P	output
K5	CLOCKDES2N	output
H4	CLOCKDES1P	output
J4	CLOCKDES1N	output
G1	CLOCKDES0P	output
H1	CLOCKDES0N	output
H6	TESTCLOCKOUT	output
P11	EFUSEPROGRAMPULSE	input
H9	STATEOVERRIDE	input
K7	CONFIGSELECT	input
N5	MODE<0>	input
L7	MODE<1>	input
L10	MODE<2>	input
P10	MODE<3>	input
M10	RESETB	input
G5	SCL	input
H5	SDA	bidirectional
P5	I2CADDRESS<3>	input
N7	I2CADDRESS<2>	input
N6	I2CADDRESS<1>	input
L8	I2CADDRESS<0>	input
N8	TCK	input
P8	TMS	input
M8	TRESETB	input
P7	TDI	input
K10	TESTOUTPUT	output
K8	LDSCL	output
H8	LDSDA	bidirectional
J7	LDRESET	output
P9	TDO	output
N11	TXDATAVALID	input
L13	TXRDY	output
E1	TXOUTP	output
D1	TXOUTN	output
M9	RXLOCKMODE<1>	input
J8	RXLOCKMODE<0>	input
T1	RXINP	input
U1	RXINN	input
N9	RXDATAVALID	output
N10	RXRDY	output
G14	VDD	power_in
G15	VDD	power_in
H13	VDD	power_in
H14	VDD	power_in
J12	VDD	power_in
J13	VDD	power_in
J14	VDD	power_in
K13	VDD	power_in
K14	VDD	power_in
L14	VDD	power_in
B10	VDDIO	power_in
B19	VDDIO	power_in
C14	VDDIO	power_in
F9	VDDIO	power_in
F19	VDDIO	power_in
K20	VDDIO	power_in
M13	VDDIO	power_in
M14	VDDIO	power_in
N12	VDDIO	power_in
N13	VDDIO	power_in
N14	VDDIO	power_in
R13	VDDIO	power_in
R18	VDDIO	power_in
W5	VDDIO	power_in
W10	VDDIO	power_in
W14	VDDIO	power_in
W18	VDDIO	power_in
A19	GND	power_in
B9	GND	power_in
C13	GND	power_in
F10	GND	power_in
F11	GND	power_in
F12	GND	power_in
F17	GND	power_in
G10	GND	power_in
G11	GND	power_in
G12	GND	power_in
G13	GND	power_in
H10	GND	power_in
H11	GND	power_in
H12	GND	power_in
J10	GND	power_in
J11	GND	power_in
J20	GND	power_in
K11	GND	power_in
K12	GND	power_in
L11	GND	power_in
L12	GND	power_in
M11	GND	power_in
M12	GND	power_in
P18	GND	power_in
R14	GND	power_in
W4	GND	power_in
W9	GND	power_in
W13	GND	power_in
W17	GND	power_in
G2	VDDPS	power_in
H3	VDDPS	power_in
J6	VDDPS	power_in
K6	VDDPS	power_in
K9	VDDPS	power_in
N4	VDDPS	power_in
H2	GNDPS	power_in
J5	GNDPS	power_in
L6	GNDPS	power_in
L9	GNDPS	power_in
N3	GNDPS	power_in
R2	VDDRX	power_in
R3	VDDRX	power_in
T3	VDDRX	power_in
U3	VDDRX	power_in
V2	VDDRX	power_in
R1	GNDRX	power_in
T2	GNDRX	power_in
U2	GNDRX	power_in
V1	GNDRX	power_in
C3	VDDTX	power_in
D3	VDDTX	power_in
E3	VDDTX	power_in
F2	VDDTX	power_in
F3	VDDTX	power_in
C1	GNDTX	power_in
C2	GNDTX	power_in
D2	GNDTX	power_in
E2	GNDTX	power_in
F1	GNDTX	power_in
J3	VDDCM	power_in
K3	VDDCM	power_in
L3	VDDCM	power_in
M3	VDDCM	power_in
J1	GNDCM	power_in
K2	GNDCM	power_in
L2	GNDCM	power_in
M1	GNDCM	power_in
P14	EFUSEPOWER	power_in
G17	UNUSED	passive

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

Comments

Loading comments...

CERN_GBTX ASIC_V0.1

Schematic Symbol

Pin Configuration (400 pins)

Footprint

Comments

Details