CERN_LPGBT_ASIC_V2

CERN LPGBT ASIC V2

Schematic Symbol

Pin Configuration (289 pins)

Pin	Name	Type
T5	EDIN00P	input
U5	EDIN00N	input
T6	EDIN01P	input
U6	EDIN01N	input
T7	EDIN02P	input
U7	EDIN02N	input
T8	EDIN03P	input
U8	EDIN03N	input
T11	EDIN10P	input
U11	EDIN10N	input
T12	EDIN11P	input
U12	EDIN11N	input
T13	EDIN12P	input
U13	EDIN12N	input
T14	EDIN13P	input
U14	EDIN13N	input
P16	EDIN20P	input
P17	EDIN20N	input
N16	EDIN21P	input
N17	EDIN21N	input
M16	EDIN22P	input
M17	EDIN22N	input
L16	EDIN23P	input
L17	EDIN23N	input
H16	EDIN30P	input
H17	EDIN30N	input
G16	EDIN31P	input
G17	EDIN31N	input
F16	EDIN32P	input
F17	EDIN32N	input
E16	EDIN33P	input
E17	EDIN33N	input
B14	EDIN40P	input
A14	EDIN40N	input
B13	EDIN41P	input
A13	EDIN41N	input
B12	EDIN42P	input
A12	EDIN42N	input
B11	EDIN43P	input
A11	EDIN43N	input
B10	EDIN50P	input
A10	EDIN50N	input
B9	EDIN51P	input
A9	EDIN51N	input
B8	EDIN52P	input
A8	EDIN52N	input
B7	EDIN53P	input
A7	EDIN53N	input
B6	EDIN60P	input
A6	EDIN60N	input
B5	EDIN61P	input
A5	EDIN61N	input
B4	EDIN62P	input
A4	EDIN62N	input
B3	EDIN63P	input
A3	EDIN63N	input
P5	EDOUT00P	output
R5	EDOUT00N	output
P6	EDOUT01P	output
R6	EDOUT01N	output
P7	EDOUT02P	output
R7	EDOUT02N	output
P8	EDOUT03P	output
R8	EDOUT03N	output
P9	EDOUT10P	output
R9	EDOUT10N	output
P10	EDOUT11P	output
R10	EDOUT11N	output
P11	EDOUT12P	output
R11	EDOUT12N	output
P12	EDOUT13P	output
R12	EDOUT13N	output
D13	EDOUT20P	output
C13	EDOUT20N	output
D12	EDOUT21P	output
C12	EDOUT21N	output
D11	EDOUT22P	output
C11	EDOUT22N	output
D10	EDOUT23P	output
C10	EDOUT23N	output
D9	EDOUT30P	output
C9	EDOUT30N	output
D8	EDOUT31P	output
C8	EDOUT31N	output
D7	EDOUT32P	output
C7	EDOUT32N	output
D6	EDOUT33P	output
C6	EDOUT33N	output
T4	ECLK0P	output
U4	ECLK0N	output
P4	ECLK1P	output
R4	ECLK1N	output
T9	ECLK2P	output
U9	ECLK2N	output
T10	ECLK3P	output
U10	ECLK3N	output
P13	ECLK4P	output
R13	ECLK4N	output
P14	ECLK5P	output
R14	ECLK5N	output
T15	ECLK6P	output
U15	ECLK6N	output
P15	ECLK7P	output
R15	ECLK7N	output
N14	ECLK8P	output
N15	ECLK8N	output
M14	ECLK9P	output
M15	ECLK9N	output
L14	ECLK10P	output
L15	ECLK10N	output
K16	ECLK11P	output
K17	ECLK11N	output
J16	ECLK12P	output
J17	ECLK12N	output
K14	ECLK13P	output
K15	ECLK13N	output
J14	ECLK14P	output
J15	ECLK14N	output
H14	ECLK15P	output
H15	ECLK15N	output
G14	ECLK16P	output
G15	ECLK16N	output
F14	ECLK17P	output
F15	ECLK17N	output
E14	ECLK18P	output
E15	ECLK18N	output
D16	ECLK19P	output
D17	ECLK19N	output
D14	ECLK20P	output
D15	ECLK20N	output
C16	ECLK21P	output
C17	ECLK21N	output
B16	ECLK22P	output
B17	ECLK22N	output
A16	ECLK23P	output
A17	ECLK23N	output
C14	ECLK24P	output
C15	ECLK24N	output
B15	ECLK25P	output
A15	ECLK25N	output
D5	ECLK26P	output
C5	ECLK26N	output
D4	ECLK27P	output
C4	ECLK27N	output
M4	PSCLK0P	output
N4	PSCLK0N	output
M5	PSCLK1P	output
N5	PSCLK1N	output
M6	PSCLK2P	output
N6	PSCLK2N	output
M7	PSCLK3P	output
N7	PSCLK3N	output
A2	ADC0	passive
A1	ADC1	passive
B2	ADC2	passive
B1	ADC3	passive
C3	ADC4	passive
C2	ADC5	passive
C1	ADC6	passive
D1	ADC7	passive
N13	GPIO0	bidirectional
N12	GPIO1	bidirectional
M11	GPIO2	bidirectional
N11	GPIO3	bidirectional
M10	GPIO4	bidirectional
N10	GPIO5	bidirectional
L9	GPIO6	bidirectional
M9	GPIO7	bidirectional
N9	GPIO8	bidirectional
L8	GPIO9	bidirectional
M8	GPIO10	bidirectional
N8	GPIO11	bidirectional
L7	GPIO12	bidirectional
L6	GPIO13	bidirectional
L5	GPIO14	bidirectional
R3	GPIO15	bidirectional
T17	EDINECP	input
U17	EDINECN	input
D2	VDAC	output
E7	M0SCL	output
F7	M0SDA	bidirectional
E6	M1SCL	output
F6	M1SDA	bidirectional
E5	M2SCL	output
F5	M2SDA	bidirectional
T2	RSTOUTB	output
T16	ECLK28P	output
U16	ECLK28N	output
R16	EDOUTECP	output
R17	EDOUTECN	output
L1	HSINP	input
M1	HSINN	input
H1	HSOUTP	output
G1	HSOUTN	output
K4	RSV1	input
L4	RSV0	input
F13	TSTOUT0	output
F12	TSTOUT1	output
F11	TSTOUT2	output
F10	TSTOUT3	output
E13	TSTOUT4P	output
E12	TSTOUT4N	output
E11	TSTOUT5P	output
E10	TSTOUT5N	output
D3	RSTB	input
E9	ADR0	input
F9	ADR1	input
E8	ADR2	input
F8	ADR3	input
G5	MODE0	input
K5	MODE1	input
P3	MODE2	input
P2	MODE3	input
R1	REFCLKP	input
P1	REFCLKN	input
E1	LOCKMODE	input
E2	EDINECTERM	input
T1	PORDIS	input
T3	BOOTCNF1	input
U1	BOOTCNF0	input
R2	READY	output
U2	SLSCL	input
U3	SLSDA	bidirectional
J5	VDD1V2	power_in
J6	VDD1V2	power_in
J7	VDD1V2	power_in
J8	VDD1V2	power_in
J9	VDD1V2	power_in
J11	VDD1V2	power_in
K6	VDD1V2	power_in
K7	VDD1V2	power_in
K8	VDD1V2	power_in
K9	VDD1V2	power_in
K11	VDD1V2	power_in
K12	VDD1V2	power_in
K13	VDD1V2	power_in
L10	VDD1V2	power_in
L11	VDD1V2	power_in
L12	VDD1V2	power_in
L13	VDD1V2	power_in
M12	VDD1V2	power_in
M13	VDD1V2	power_in
G6	GND	power_in
G7	GND	power_in
G8	GND	power_in
G9	GND	power_in
G10	GND	power_in
G11	GND	power_in
G12	GND	power_in
G13	GND	power_in
H5	GND	power_in
H6	GND	power_in
H7	GND	power_in
H8	GND	power_in
H9	GND	power_in
H10	GND	power_in
H11	GND	power_in
H12	GND	power_in
H13	GND	power_in
J12	GND	power_in
J13	GND	power_in
K3	VDDRX1V2	power_in
L3	VDDRX1V2	power_in
M3	VDDRX1V2	power_in
N3	VDDRX1V2	power_in
K1	GNDRX	power_in
K2	GNDRX	power_in
L2	GNDRX	power_in
M2	GNDRX	power_in
N1	GNDRX	power_in
N2	GNDRX	power_in
F3	VDDTX1V2	power_in
G3	VDDTX1V2	power_in
H3	VDDTX1V2	power_in
J3	VDDTX1V2	power_in
F1	GNDTX	power_in
F2	GNDTX	power_in
G2	GNDTX	power_in
H2	GNDTX	power_in
J1	GNDTX	power_in
J2	GNDTX	power_in
E4	VDDA1V2	power_in
E3	VDDA1V2	power_in
F4	GNDA	power_in
G4	GNDA	power_in
J10	VDDF2V5	power_in
K10	VDDF2V5	power_in
J4	VREF	power_in
H4	VREF	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

Comments

Loading comments...

CERN_LPGBT_ASIC_V2

Schematic Symbol

Pin Configuration (289 pins)

Footprint

Comments

Details