CERN_TOP_Utopia_V1.0

Synchronous Charge to Frequency Converter (CFC) Architecture Tester (Asic developed at CERN)

Schematic Symbol

Pin Configuration (39 pins)

Pin	Name	Type
40	VCM	input
41	Vcharge	input
42	Ibias_ota	input
43	init	input
44	Ibias_buf	input
1	Ibias_comp	input
2	Vref	input
3	gnd	power_in
4	O_ANAL1	output
39	gnd	power_in
7	O_DIG1	output
38	IN1	input
8	CLK1	input
36	IN2	input
9	O_ANAL2	output
34	IN3	input
10	O_DIG2	output
33	SW	input
11	CLK2	input
32	IN4	input
12	O_ANAL3	output
31	VDDA	power_in
13	O_DIG3	output
30	G_n	bidirectional
14	CLK3	input
29	S_n	bidirectional
15	O_ANAL4	output
28	D_n	bidirectional
16	O_DIG4	output
27	D_p	bidirectional
26	S_p	bidirectional
25	G_p	bidirectional
24	gnd	power_in
23	VDDD	power_in
22	FF_in	input
21	CLK4	input
20	FF_out	output
19	NOC_in	input
18	gnd	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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