DP83822

Robust, Low Power 10/100 Mbps Ethernet Physical Layer Transceiver

Schematic Symbol

Pin Configuration (33 pins)

Pin	Name	Type
19	MDIO	bidirectional
20	MDC	input
12	TD_P	output
11	TD_M	output
10	RD_P	input
9	RD_M	input
2	TX_CLK	bidirectional
3	TX_EN/TX_CTRL	input
4	TX_D0	input
5	TX_D1	input
6	TX_D2	input
7	TX_D3	input
21	VDDIO	power_in
14	AVD	power_in
24	GPIO1/LED_1	bidirectional
17	LED_0	output
22	XO	output
23	XI	input
8	~{INT}/~{PWDN}	bidirectional
18	~{RESET}	input
27	CRS/CRS_DV	output
29	GPIO2/COL	bidirectional
16	RBIAS	passive
25	RX_CLK	output
26	RX_DV/RX_CTRL	output
28	RX_ER	bidirectional
30	RX_D0	output
31	RX_D1	output
32	RX_D2	output
1	GPIO3/RX_D3	bidirectional
13	NC	passive
15	NC	passive
33	EP_(GND)	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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