DP83867

Robust, High Immunity, Small Form Factor 10/100/1000 Ethernet Physical Layer Transceiver

Schematic Symbol

Pin Configuration (49 pins)

Pin	Name	Type
17	MDIO	bidirectional
16	MDC	input
20	JTAG_CLK	input
21	JTAG_TDO	output
22	JTAG_TMS	input
23	JTAG_TDI	input
29	GTX_CLK	input
37	TX_CTRL	input
28	TX_D0/SGMII_SIN	input
27	TX_D1/SGMII_SIP	input
26	TX_D2	input
25	TX_D3	input
19	VDDIO	power_in
30	VDDIO	power_in
41	VDDIO	power_in
6	VDD1P0	power_in
24	VDD1P0	power_in
31	VDD1P0	power_in
42	VDD1P0	power_in
3	VDDA2P5	power_in
9	VDDA2P5	power_in
13	VDDA1P8	power_in
48	VDDA1P8	power_in
45	LED_2	bidirectional
46	LED_1	bidirectional
47	LED_0	bidirectional
14	X_O	output
15	X_I	input
18	CLK_OUT	output
44	~{INT}/~{PWDN}	bidirectional
43	RESET_N	input
12	RBIAS	passive
32	RX_CLK	output
38	RX_CTRL	output
36	RX_D3/SGMII_SON	output
35	RX_D2/SGMII_SOP	output
34	RX_D1/SGMII_CON	output
33	RX_D0/SGMII_COP	output
1	TD_P_A	bidirectional
2	TD_N_A	bidirectional
4	TD_P_B	bidirectional
5	TD_N_B	bidirectional
7	TD_P_C	bidirectional
8	TD_N_C	bidirectional
10	TD_P_D	bidirectional
11	TD_N_D	bidirectional
40	GPIO_1	output
39	GPIO_0	output
49	EP_(GND)	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

Comments

Loading comments...

Sign in to leave a comment.