DP83869HMRGZ

DP83869HM High Immunity 10/100/1000 Ethernet Physical Layer Transceiver WithCopper and Fiber Interface

Schematic Symbol

Pin Configuration (49 pins)

Pin	Name	Type
41	MDIO	bidirectional
42	MDC	input
21	JTAG_CLK/TX_ER	input
22	JTAG_TDO/GPIO_1	output
23	JTAG_TMS	input
24	JTAG_TDI/SD	input
15	SOP	output
14	SON	output
16	SIP	input
17	SIN	input
29	GTX_CLK/TX_CLK	bidirectional
37	TX_CTRL/TX_EN	input
28	TX_D0	input
27	TX_D1	input
26	TX_D2	input
25	TX_D3	input
18	VDDIO	power_in
30	VDDIO	power_in
6	VDD1P1	power_in
31	VDD1P1	power_in
39	VDD1P1	power_in
3	VDDA2P5	power_in
9	VDDA2P5	power_in
13	VDDA1P8_1	power_in
48	VDDA1P8_2	power_in
45	LED_2/GPIO_0	bidirectional
46	LED_1/RX_ER	output
47	LED_0	output
19	XO	output
20	XI	input
40	CLK_OUT	output
44	INT_N/PWDN_N	bidirectional
43	RESET_N	input
12	RBIAS	passive
32	RX_CLK	output
38	RX_CTRL/RX_DV	output
36	RX_D3	output
35	RX_D2	output
34	RX_D1	output
33	RX_D0	output
1	TD_P_A	bidirectional
2	TD_M_A	bidirectional
4	TD_P_B	bidirectional
5	TD_M_B	bidirectional
7	TD_P_C	bidirectional
8	TD_M_C	bidirectional
10	TD_P_D	bidirectional
11	TD_M_D	bidirectional
49	EP_(GND)	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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