DS25BR440

3.125-Gbps Quad LVDS Buffer with Transmit Pre-Emphasis and Receive Equalization

Schematic Symbol

Pin Configuration (41 pins)

Pin	Name	Type
31	PE0	input
1	IN0+	input
2	IN0-	input
40	EQ0	input
35	~{PWDN0}	input
20	PE1	input
4	IN1+	input
5	IN1-	input
39	EQ1	input
34	~{PWDN1}	input
19	PE2	input
6	IN2+	input
7	IN2-	input
11	EQ2	input
33	~{PWDN2}	input
18	PE3	input
9	IN3+	input
10	IN3-	input
12	EQ3	input
32	~{PWDN3}	input
38	~{PWDN}	input
3	VDD	power_in
8	VDD	power_in
15	VDD	power_in
25	VDD	power_in
30	VDD	power_in
29	OUT0+	output
28	OUT0-	output
14	~{LOS0}	output
27	OUT1+	output
26	OUT1-	output
37	~{LOS1}	output
24	OUT2+	output
23	OUT2-	output
36	~{LOS2}	output
22	OUT3+	output
21	OUT3-	output
13	~{LOS3}	output
17	NC	passive
16	GND	power_in
41	EP(GND)	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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