LMK00304

3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator

Schematic Symbol

Pin Configuration (33 pins)

Pin	Name	Type
9	CLKOUT_TYPE0	output
32	CLKOUT_TYPE1	input
13	CLKIN_SEL0	input
16	CLKIN_SEL	input
14	CLKIN0	input
15	~{CLKIN0}	input
26	~{CLKIN1}	input
27	CLKIN1	input
11	OSCIN	input
12	OSCOUT	output
31	REFOUT_EN	input
10	VCC	power_in
28	VCC	power_in
2	VCCOA	power_in
5	VCCOA	power_in
20	VCCOB	power_in
23	VCCOB	power_in
30	VCCOC	power_in
3	CLKOUTA0	output
4	~{CLKOUTA0}	output
6	CLKOUTA1	output
7	~{CLKOUTA1}	output
22	CLKOUTB0	output
21	~{CLKOUTB0}	output
19	CLKOUTB1	output
18	~{CLKOUTB}1	output
29	REFOUT	output
25	NC	passive
1	GND	power_in
8	GND	power_in
17	GND	power_in
24	GND	power_in
33	GND	power_in

Footprint

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