LMK03318RHS

Ultra-Low-Noise Jitter Clock Generator Family With One PLL, Eight Outputs, Integrated EEPROM

Schematic Symbol

Pin Configuration (49 pins)

Pin	Name	Type
12	GPIO0	input
24	GPIO1	input
30	GPIO2	input
31	GPIO3	input
32	GPIO4	input
33	GPIO5	input
25	SDA	bidirectional
26	SCL	input
9	HW_SW_CTRL	input
13	PDN	input
6	PRIREF_P	input
7	PRIREF_N	input
10	SECREF_P	input
11	SECREF_N	input
8	REFSEL	input
1	STATUS0	output
2	STATUS1	output
4	VDD_DIG	power_in
5	VDD_IN	power_in
27	VDD_LDO	power_in
36	VDD_PLL	power_in
18	VDDO_01	power_in
19	VDDO_23	power_in
37	VDDO_4	power_in
40	VDDO_5	power_in
43	VDDO_6	power_in
46	VDDO_7	power_in
14	OUT0_P	output
15	OUT0_N	output
17	OUT1_P	output
16	OUT1_N	output
20	OUT2_P	output
21	OUT2_N	output
23	OUT3_P	output
22	OUT3_N	output
39	OUT4_P	output
38	OUT4_N	output
42	OUT5_P	output
41	OUT5_N	output
45	OUT6_P	output
44	OUT6_N	output
48	OUT7_P	output
47	OUT7_N	output
34	LF	passive
3	CAP_DIG	passive
28	CAP_LDO	passive
35	CAP_PLL	passive
29	NC	passive
49	EP	passive

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

Comments

Loading comments...

Sign in to leave a comment.