LTC6952

Ultralow Jitter, Clock Generation and Distribution with 4.5GHz PLL

Schematic Symbol

Pin Configuration (53 pins)

Pin	Name	Type
37	VCO+	input
38	VCO-	input
43	CP	output
45	REF+	input
46	REF-	input
47	EZS_SRQ+	input
48	EZS_SRQ-	input
49	STAT	output
50	SCLK	input
52	SDI	input
51	SDO	output
1	~{CS}	input
40	~{SD}	input
39	VVCO+	power_in
42	VCP+	power_in
44	VREF+	power_in
36	NC	passive
2	VD+	power_in
41	GND	power_in
53	GND	power_in
34	OUT0+	output
33	OUT0-	output
31	OUT1+	output
30	OUT1-	output
28	OUT2+	output
27	OUT2-	output
25	OUT3+	output
24	OUT3-	output
22	OUT4+	output
21	OUT4-	output
19	OUT5+	output
18	OUT5-	output
16	OUT6+	output
15	OUT6-	output
12	OUT7-	output
13	OUT7+	output
9	OUT8-	output
10	OUT8+	output
6	OUT9-	output
7	OUT9+	output
3	OUT10-	output
4	OUT10+	output
35	VOUT+	power_in
32	VOUT+	power_in
29	VOUT+	power_in
26	VOUT+	power_in
23	VOUT+	power_in
20	VOUT+	power_in
17	VOUT+	power_in
14	VOUT+	power_in
11	VOUT+	power_in
8	VOUT+	power_in
5	VOUT+	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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