SI53312

2 Input/10 Output, Low Jitter Universal Buffer/Level Translator With 2:1 Input Mux (<1.25 GHZ)

Schematic Symbol

Pin Configuration (45 pins)

Pin	Name	Type
1	DIVA	input
16	OEA	input
2	SFOUTA1	input
3	SFOUTA0	input
14	CLK0	input
15	~{CLK0}	input
19	CLK1	input
20	~{CLK1}	input
23	CLK_SEL	input
17	VREF	input
33	DIVB	input
18	OEB	input
32	SFOUTB1	input
31	SFOUTB0	input
12	VDD	power_in
6	GND	power_in
22	GND	power_in
39	GND	power_in
45	GND	power_in
10	Q0	output
9	~{Q0}	output
8	Q1	output
7	~{Q1}	output
5	Q2	output
4	~{Q2}	output
43	Q3	output
42	~{Q3}	output
41	Q4	output
40	~{Q4}	output
38	Q5	output
37	~{Q5}	output
36	Q6	output
35	~{Q6}	output
30	Q7	output
29	~{Q7}	output
27	Q8	output
26	~{Q8}	output
25	Q9	output
24	~{Q9}	output
11	NC	passive
13	NC	passive
21	NC	passive
28	NC	passive
44	VDDOA	output
34	VDDOB	output

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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