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Si53307
Low-Jitter Universal Buffer/Level Translator
Schematic Symbol
Pin Configuration (17 pins)
| Pin | Name | Type |
|---|---|---|
| 6 | CLK0 | input |
| 7 | ~{CLK0} | input |
| 2 | CLK1 | input |
| 3 | ~{CLK1} | input |
| 14 | CLK_SEL | input |
| 16 | OE | input |
| 13 | SFOUT0 | input |
| 8 | SFOUT1 | input |
| 5 | VDDO | power_in |
| 12 | Q0 | output |
| 11 | ~{Q0} | output |
| 10 | Q1 | output |
| 9 | ~{Q1} | output |
| 1 | VDD | power_in |
| 15 | GND | power_in |
| 4 | GND | power_in |
| 17 | GND | power_in |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.