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STGAP1AS

Galvanically isolated 5 A advanced single gate driver, Dual Output, Miller Clamp, Sense, Desaturation, UVLO, OVLO, SPI, AEC-Q100, SOIC-24

Schematic Symbol

STGAP1ASGNDSDI~{CS}CKVDDIN+~{SD}GNDGNDISOVLSENSEVHDESATVCECLAMPVLASCSDOVREGIN-/DIAG2DIAG1VREGISOGONGOFFCLAMP

Pin Configuration (24 pins)

PinNameType
1GNDpower_in
2SDOoutput
3SDIinput
4~{CS}input
5CKinput
6VREGpower_out
7VDDpower_in
8IN-/DIAG2bidirectional
9IN+input
10DIAG1open_collector
11~{SD}input
12GNDpassive
13GNDISOpower_in
14VLpower_in
15VREGISOpower_out
16SENSEinput
17VHpower_in
18DESATpassive
19VCECLAMPinput
20GONoutput
21GOFFoutput
22CLAMPoutput
23VLpassive
24ASCinput

Footprint

Confirmed

Package_SO/SOIC-24W_7.5x15.4mm_P1.27mm

Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pads (24)
NumberType
1smd
2smd
3smd
4smd
5smd
6smd
7smd
8smd
9smd
10smd
11smd
12smd
13smd
14smd
15smd
16smd
17smd
18smd
19smd
20smd
21smd
22smd
23smd
24smd

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Footprint

Details

LibraryDriver_FET
Pin Count24
FootprintSOIC-24W_7.5x15.4mm_P1.27mm
Pad Count24
View Datasheet
STGAP1AS — Driver_FET | Trace Components