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DP83848I

MII/RMII Single 10/100Mbps Ethernet Physical Layer Transceiver, LQFP-48

Schematic Symbol

DP83848ITX_ENTXD_0TXD_1TXD_2TXD_3/SNI_MODEPWR_DOWN/INTRD-RD+AGNDTD-TD+PFBIN1AGNDRESERVEDRESERVEDAVDD33PFBOUTRBIAS~{RESET}MDCIOVDD33X1IOGNDDGNDPFBIN2IOGNDIOVDD33TX_CLK25M_OUTAN_EN/LED_ACT/COLAN1/LED_SPEEDAN0/LED_LINKMDIOX2RX_CLKRX_DV/MII_MODECRS/CRS_DV/LED_CFGRX_ER/MDIX_ENCOL/PHY_AD0RXD_0/PHY_AD1RXD_1/PHY_AD2RXD_2/PHY_AD3RXD_3/PHY_AD4

Pin Configuration (43 pins)

PinNameType
1TX_CLKoutput
2TX_ENinput
3TXD_0input
4TXD_1input
5TXD_2input
6TXD_3/SNI_MODEinput
7PWR_DOWN/INTinput
13RD-passive
14RD+passive
15AGNDpower_in
16TD-passive
17TD+passive
18PFBIN1passive
19AGNDpassive
20RESERVEDpassive
21RESERVEDpassive
22AVDD33power_in
23PFBOUTpassive
24RBIASpassive
2525M_OUToutput
26AN_EN/LED_ACT/COLoutput
27AN1/LED_SPEEDoutput
28AN0/LED_LINKoutput
29~{RESET}input
30MDIObidirectional
31MDCinput
32IOVDD33power_in
33X2output
34X1input
35IOGNDpower_in
36DGNDpower_in
37PFBIN2passive
38RX_CLKoutput
39RX_DV/MII_MODEoutput
40CRS/CRS_DV/LED_CFGoutput
41RX_ER/MDIX_ENoutput
42COL/PHY_AD0output
43RXD_0/PHY_AD1output
44RXD_1/PHY_AD2output
45RXD_2/PHY_AD3output
46RXD_3/PHY_AD4output
47IOGNDpassive
48IOVDD33passive

Footprint

Confirmed

Package_QFP/LQFP-48_7x7mm_P0.5mm

Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pads (48)
NumberType
1smd
2smd
3smd
4smd
5smd
6smd
7smd
8smd
9smd
10smd
11smd
12smd
13smd
14smd
15smd
16smd
17smd
18smd
19smd
20smd
21smd
22smd
23smd
24smd
25smd
26smd
27smd
28smd
29smd
30smd
31smd
32smd
33smd
34smd
35smd
36smd
37smd
38smd
39smd
40smd
41smd
42smd
43smd
44smd
45smd
46smd
47smd
48smd

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Footprint

Details

Pin Count43
FootprintLQFP-48_7x7mm_P0.5mm
Pad Count48
View Datasheet