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LAN9303
3-port managed Ethernet switch with dual PHY and RMII interface, QFN-56
Schematic Symbol
Pin Configuration (57 pins)
| Pin | Name | Type |
|---|---|---|
| 1 | TXN2 | bidirectional |
| 2 | P0_IND3 | passive |
| 3 | P0_IND2 | passive |
| 4 | P0_IND1 | input |
| 5 | P0_IND0 | input |
| 6 | P0_INDV | input |
| 7 | P0_INER | passive |
| 8 | P0_INCLK | passive |
| 9 | VDD33IO | power_in |
| 10 | VDD18CORE | output |
| 11 | P0_OUTD3/~{DUPLEX_POL_0} | passive |
| 12 | P0_OUTD2/~{P0_MODE2} | passive |
| 13 | P0_OUTD1/~{P0_MODE1} | bidirectional |
| 14 | P0_OUTD0/~{P0_MODE0} | bidirectional |
| 15 | VDD33IO | passive |
| 16 | P0_OUTDV | output |
| 17 | P0_OUTCLK | bidirectional |
| 18 | P0_COL | passive |
| 19 | P0_CRS | passive |
| 20 | P0_DUPLEX | input |
| 21 | MDIO | bidirectional |
| 22 | MDC | bidirectional |
| 23 | VDD33IO | passive |
| 24 | LED5/GPIO5/~{PHYADDR} | passive |
| 25 | LED4/GPIO4/~{MNGT1} | passive |
| 26 | LED3/GPIO3/~{MNGT0} | passive |
| 27 | LED2/GPIO2/~{E2PSIZE} | passive |
| 28 | LED1/GPIO1/~{AMDIX2} | passive |
| 29 | LED0/GPIO0/~{AMDIX1} | passive |
| 30 | VDD33IO | passive |
| 31 | VDD18CORE | passive |
| 32 | VDD33IO | passive |
| 33 | VDD33IO | passive |
| 34 | VSS | power_in |
| 35 | EE_SDA/SDA | bidirectional |
| 36 | EE_SCL/SCL | bidirectional |
| 37 | ~{RST} | passive |
| 38 | IRQ | passive |
| 39 | XI | input |
| 40 | XO | passive |
| 41 | VDD18PLL | output |
| 42 | TXN1 | bidirectional |
| 43 | TXP1 | bidirectional |
| 44 | VDD33A1 | power_in |
| 45 | RXN1 | bidirectional |
| 46 | RXP1 | bidirectional |
| 47 | VDD33A1 | passive |
| 48 | VDD18TX1 | input |
| 49 | EXRES | passive |
| 50 | VDD33BIAS | power_in |
| 51 | VDD18TX2 | output |
| 52 | VDD33A2 | power_in |
| 53 | RXP2 | bidirectional |
| 54 | RXN2 | bidirectional |
| 55 | VDD33A2 | passive |
| 56 | TXP2 | bidirectional |
| 57 | VSS | passive |
Footprint
ConfirmedPackage_DFN_QFN/QFN-56-1EP_8x8mm_P0.5mm_EP5.9x5.9mm_ThermalVias
Pad Layout
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Pads (99)
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| — | smd |
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| 57 | thru hole |
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| 57 | smd |
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