Back to browse

CDCLVP1102RGT

Two-LVPECL Output, High-Performance Clock Buffer, VQFN-16

Schematic Symbol

CDCLVP1102RGTGNDVCCINPINNGNDGNDNCNCNCVAC_REFOUTP0OUTN0OUTP1OUTN1NCNCNC

Pin Configuration (17 pins)

PinNameType
1GNDpower_in
2NCno_connect
3NCno_connect
4NCno_connect
5VCCpower_in
6INPinput
7INNinput
8VAC_REFoutput
9OUTP0output
10OUTN0output
11OUTP1output
12OUTN1output
13NCno_connect
14NCno_connect
15NCno_connect
16GNDpassive
17GNDpassive

Footprint

Confirmed

Package_DFN_QFN/VQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias

Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
17
17
17
17
17
Pads (26)
NumberType
smd
smd
smd
smd
1smd
2smd
3smd
4smd
5smd
6smd
7smd
8smd
9smd
10smd
11smd
12smd
13smd
14smd
15smd
16smd
17thru hole
17thru hole
17smd
17smd
17thru hole
17thru hole

Comments

Loading comments...

Sign in to leave a comment.

SymbolDownload Library
Footprint

Details

LibraryInterface
Pin Count17
FootprintVQFN-16-1EP_3x3mm_P0.5mm_EP1.6x1.6mm_ThermalVias
Pad Count26
View Datasheet