AD9510

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Schematic Symbol

Pin Configuration (65 pins)

Pin	Name	Type
14	CLK1	input
15	CLK1B	input
10	CLK2	input
11	CLK2B	input
1	REFIN	input
2	REFINB	input
18	SCLK	input
21	CSB	input
19	SDIO	bidirectional
20	SDO	output
16	FUNCTION	input
17	STATUS	output
63	CPRSET	input
61	RSET	input
4	VS	power_in
9	VS	power_in
13	VS	power_in
23	VS	power_in
26	VS	power_in
30	VS	power_in
31	VS	power_in
33	VS	power_in
36	VS	power_in
37	VS	power_in
40	VS	power_in
41	VS	power_in
44	VS	power_in
45	VS	power_in
48	VS	power_in
51	VS	power_in
52	VS	output
56	VS	power_in
59	VS	power_in
60	VS	power_in
64	VS	power_in
58	OUT0	output
57	OUT0B	output
54	OUT1	output
53	OUT1B	output
35	OUT2	output
34	OUT2B	output
29	OUT3	output
28	OUT3B	output
47	OUT4	output
46	OUT4B	output
43	OUT5	output
42	OUT5B	output
39	OUT6	output
38	OUT6B	output
25	OUT7	output
24	OUT7B	output
6	CP	output
5	VCP	power_in
3	GND	power_in
7	GND	power_in
8	GND	power_in
12	GND	power_in
22	GND	power_in
27	GND	power_in
32	GND	power_in
49	GND	power_in
50	GND	power_in
55	GND	power_in
62	GND	power_in
65	EP	power_in

Footprint

This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.

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