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AD9520-0
12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO
Schematic Symbol
Pin Configuration (65 pins)
| Pin | Name | Type |
|---|---|---|
| 3 | LD | output |
| 6 | STATUS | output |
| 2 | REFMON | output |
| 7 | REF_SEL | input |
| 62 | CPRESET | output |
| 58 | RSET | passive |
| 9 | LF | input |
| 5 | CP | output |
| 10 | BYPASS | passive |
| 64 | REFIN(REF1) | input |
| 63 | ~{REFIN}(REF2) | input |
| 13 | CLK | input |
| 14 | ~{CLK} | input |
| 24 | ~{PD} | input |
| 8 | ~{SYNC} | input |
| 23 | ~{RESET} | input |
| 16 | SCLK/SCL | input |
| 17 | SDIO/SDA | bidirectional |
| 18 | SDO | output |
| 15 | ~{C}S | input |
| 20 | SP1 | input |
| 21 | SP0 | input |
| 22 | EEPROM | input |
| 1 | VS | power_in |
| 11 | VS | power_in |
| 12 | VS | power_in |
| 32 | VS | power_in |
| 40 | VS | power_in |
| 41 | VS | power_in |
| 49 | VS | power_in |
| 57 | VS | power_in |
| 60 | VS | power_in |
| 61 | VS | power_in |
| 65 | EP(GND) | power_in |
| 56 | OUT0 | output |
| 55 | ~{OUT0} | output |
| 53 | OUT1 | output |
| 52 | ~{OUT1} | output |
| 51 | OUT2 | output |
| 50 | ~{OUT2} | output |
| 48 | OUT3 | output |
| 47 | ~{OUT3} | output |
| 45 | OUT4 | output |
| 44 | ~{OUT4} | output |
| 43 | OUT5 | output |
| 42 | ~{OUT5} | output |
| 33 | OUT6(OUT6A) | output |
| 34 | ~{OUT6}(OUT6B) | output |
| 36 | OUT7(OUT7A) | output |
| 37 | ~{OUT7}(OUT7B) | output |
| 38 | OUT8(OUT8A) | output |
| 39 | ~{OUT8}(OUT8B) | output |
| 25 | OUT9(OUT9A) | output |
| 26 | ~{OUT9}(OUT9B) | output |
| 28 | OUT10(OUT10A) | output |
| 29 | ~{OUT10}(OUT10B) | output |
| 30 | OUT11(OUT11A) | output |
| 31 | ~{OUT11}(OUT11B) | output |
| 4 | VCP | power_in |
| 27 | VS_DRV | power_in |
| 35 | VS_DRV | power_in |
| 46 | VS_DRV | power_in |
| 54 | VS_DRV | power_in |
| 19 | GND | power_in |
| 59 | GND | power_in |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.