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AD9520-5
12 LVPECL/24 CMOS Output Clock Generator
Schematic Symbol
Pin Configuration (65 pins)
| Pin | Name | Type |
|---|---|---|
| 3 | LD | output |
| 6 | STATUS | output |
| 2 | REFMON | output |
| 7 | REF_SEL | input |
| 62 | CPRSET | input |
| 58 | RSET | input |
| 9 | NC | passive |
| 5 | CP | output |
| 10 | NC | passive |
| 64 | REFIN_(REF1) | input |
| 63 | ~{REFIN}_(REF2) | input |
| 13 | CLK | input |
| 14 | ~{CLK} | input |
| 24 | ~{PD} | input |
| 8 | ~{SYNC} | input |
| 23 | ~{RESET} | input |
| 16 | SCLK/SCL | input |
| 17 | SDIO/SDA | bidirectional |
| 18 | SDO | tri_state |
| 15 | ~{CS} | input |
| 20 | SP1 | input |
| 21 | SP0 | input |
| 22 | EEPROM | input |
| 1 | VS | power_in |
| 11 | VS | power_in |
| 12 | VS | power_in |
| 32 | VS | power_in |
| 40 | VS | power_in |
| 41 | VS | power_in |
| 49 | VS | power_in |
| 57 | VS | power_in |
| 60 | VS | power_in |
| 61 | VS | power_in |
| 65 | EP(GND) | power_in |
| 56 | OUT0_(OUT0A) | output |
| 55 | ~{OUT0}_(OUT0B) | output |
| 53 | OUT1_(OUT1A) | output |
| 52 | ~{OUT1}_(OUT1B) | output |
| 51 | OUT2_(OUT2A) | output |
| 50 | ~{OUT2}_(OUT2B) | output |
| 48 | OUT3_(OUT3A) | output |
| 47 | ~{OUT3}_(OUT3B) | output |
| 45 | OUT4_(OUT4A) | output |
| 44 | ~{OUT4}_(OUT4B) | output |
| 43 | OUT5_(OUT5A) | output |
| 42 | ~{OUT5}_(OUT5B) | output |
| 33 | OUT6_(OUT6A) | output |
| 34 | ~{OUT6}_(OUT6B) | output |
| 36 | OUT7_(OUT7A) | output |
| 37 | ~{OUT7}_(OUT7B) | output |
| 38 | OUT8_(OUT8A) | output |
| 39 | ~{OUT8}_(OUT8B) | output |
| 25 | OUT9_(OUT9A) | output |
| 26 | ~{OUT9}_(OUT9B) | output |
| 28 | OUT10_(OUT10A) | output |
| 29 | ~{OUT10}_(OUT10B) | output |
| 30 | OUT11_(OUT11A) | output |
| 31 | ~{OUT11}_(OUT11B) | output |
| 4 | VCP | power_in |
| 27 | VS_DRV | power_in |
| 35 | VS_DRV | power_in |
| 46 | VS_DRV | power_in |
| 54 | VS_DRV | power_in |
| 19 | GND | power_in |
| 59 | GND | power_in |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.