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EP1C3T100C8N
Cyclone Family, 1.5V FPGA, 65 I/O Pins, 1 x PLL, Commercial Grade, Speed Grade 8, Pb-Free
Schematic Symbol
Pin Configuration (100 pins)
| Pin | Name | Type |
|---|---|---|
| 25 | IO | bidirectional |
| 24 | IO | bidirectional |
| 23 | IO | bidirectional |
| 22 | IO | bidirectional |
| 21 | IO | bidirectional |
| 20 | IO,_VREF2B1 | bidirectional |
| 17 | IO_(ASDO) | bidirectional |
| 6 | IO_(nCSO) | bidirectional |
| 5 | IO,_VREF1B1 | bidirectional |
| 4 | IO,_VREF0B1 | bidirectional |
| 3 | IO_(CLKUSR) | bidirectional |
| 2 | IO_(CRC_ERROR) | bidirectional |
| 1 | IO_(INIT_DONE) | bidirectional |
| 100 | IO_(DEV_CLRn)/(DQ1T7) | bidirectional |
| 99 | IO_(DEV_OE)/(DQ1T6) | bidirectional |
| 98 | IO_(DQ1T5) | bidirectional |
| 97 | IO_(DQ1T4) | bidirectional |
| 92 | IO,_DPCLK2_(DQS1T) | bidirectional |
| 91 | IO,_VREF2B2 | bidirectional |
| 90 | IO_(DM1T) | bidirectional |
| 89 | IO | bidirectional |
| 88 | IO,_VREF1B2 | bidirectional |
| 87 | IO | bidirectional |
| 86 | IO | bidirectional |
| 85 | IO,_VREF0B2 | bidirectional |
| 84 | IO,_DPCLK3_(DQS0T) | bidirectional |
| 79 | IO_(DQ1T3) | bidirectional |
| 78 | IO_(DQ1T2) | bidirectional |
| 77 | IO_(DQ1T1) | bidirectional |
| 76 | IO_(DQ1T0) | bidirectional |
| 75 | IO | bidirectional |
| 74 | IO_(DQ0R0) | bidirectional |
| 73 | IO,_VREF0B3 | bidirectional |
| 72 | IO,_DPCLK4_(DQS0R) | bidirectional |
| 71 | IO_(DQ0R1) | bidirectional |
| 70 | IO_(DQ0R2) | bidirectional |
| 69 | IO_(DQ0R3) | bidirectional |
| 68 | IO,_VREF1B3 | bidirectional |
| 65 | IO_(DM0R) | bidirectional |
| 57 | IO,_VREF2B3 | bidirectional |
| 56 | IO_(DQ0R4) | bidirectional |
| 55 | IO_(DQ0R5) | bidirectional |
| 54 | IO_(DQ0R6) | bidirectional |
| 53 | IO_(DQ0R7) | bidirectional |
| 52 | IO | bidirectional |
| 51 | IO | bidirectional |
| 50 | IO_(DQ1B0) | bidirectional |
| 49 | IO_(DQ1B1) | bidirectional |
| 48 | IO_(DQ1B2) | bidirectional |
| 47 | IO_(DQ1B3) | bidirectional |
| 42 | IO,_DPCLK6_(DQS0B) | bidirectional |
| 41 | IO,_VREF0B4 | bidirectional |
| 40 | IO | bidirectional |
| 39 | IO_(DM1B) | bidirectional |
| 38 | IO,_VREF1B4 | bidirectional |
| 37 | IO | bidirectional |
| 36 | IO_(DQ1B4) | bidirectional |
| 35 | IO,_VREF2B4 | bidirectional |
| 34 | IO,_DPCLK7_(DQS1B) | bidirectional |
| 29 | IO_(DQ1B5) | bidirectional |
| 28 | IO_(DQ1B6) | bidirectional |
| 27 | IO_(DQ1B7) | bidirectional |
| 26 | IO | bidirectional |
| 67 | TDI | input |
| 64 | TDO | output |
| 62 | TCK | input |
| 63 | TMS | input |
| 16 | DCLK | bidirectional |
| 7 | DATA0 | input |
| 14 | MSEL0 | input |
| 15 | MSEL1 | input |
| 8 | nCONFIG | input |
| 13 | nCE | input |
| 60 | CONF_DONE | bidirectional |
| 61 | nSTATUS | bidirectional |
| 12 | nCEO | output |
| 18 | VCCIO1 | power_in |
| 80 | VCCIO2 | power_in |
| 95 | VCCIO2 | power_in |
| 59 | VCCIO3 | power_in |
| 31 | VCCIO4 | power_in |
| 46 | VCCIO4 | power_in |
| 33 | VCCINT | power_in |
| 44 | VCCINT | power_in |
| 82 | VCCINT | power_in |
| 93 | VCCINT | power_in |
| 19 | GND | power_in |
| 30 | GND | power_in |
| 43 | GND | power_in |
| 45 | GND | power_in |
| 81 | GND | power_in |
| 32 | GND | power_in |
| 58 | GND | power_in |
| 83 | GND | power_in |
| 94 | GND | power_in |
| 96 | GND | power_in |
| 9 | VCCA_PLL1 | power_in |
| 11 | GNDA_PLL1 | power_in |
| 10 | CLK0 | input |
| 66 | CLK2 | input |
Footprint
This symbol has no default footprint. It's typically a generic part where the footprint depends on the package you choose.