PIC18LF44J10-IP

16K Flash, 1K SRAM, ADC, DIP40

Schematic Symbol

Pin Configuration (40 pins)

Pin	Name	Type
1	~{MCLR}	input
2	RA0/AN0	tri_state
3	RA1/AN1	tri_state
4	RA2/AN2/Vref-/CVref	tri_state
5	RA3/AN3/Vref+	tri_state
6	VDDCORE/VCAP	passive
7	RA5/AN4/~{SS1}/C2OUT	tri_state
8	~{RD}/AN5/RE0	tri_state
9	~{WR}/AN6/RE1	tri_state
10	~{CS}/AN7/RE2	tri_state
11	VDD	power_in
12	VSS	power_in
13	OSC1/CLKI	input
14	OSC2/CLK0	output
15	T1OSO/T1CKI/RC0	tri_state
16	T1OSI/CCP2/RC1	tri_state
17	P1A/CCP1/RC2	tri_state
18	SCK1/SCL1/RC3	tri_state
19	PSP0/SCK2/SCL2/RD0	tri_state
20	PSP1/SDI2/SDA2/RD1	tri_state
21	PSP2/SDO2/RD2	tri_state
22	PSP3/~{SS2}/RD3	tri_state
23	SDI1/SDA1/RC4	tri_state
24	SDO1/RC5	tri_state
25	TX/CK/RC6	tri_state
26	RX/DT/RC7	tri_state
27	PSP4/RD4	tri_state
28	PSP5/P1B/RD5	tri_state
29	PSP6/P1C/RD6	tri_state
30	PSP7/P1D/RD7	tri_state
31	VSS	power_in
32	VDD	power_in
33	RB0/INT0/FLT0/AN12	tri_state
34	RB1/INT1/AN10	tri_state
35	RB2/INT2/AN8	tri_state
36	RB3/CCP2/AN9	tri_state
37	RB4/KBI0/AN11	tri_state
38	RB5/KBI1/T0CKI/C1OUT	tri_state
39	RB6/KBI2/PGC	tri_state
40	RB7/KBI3/PGD	tri_state

Footprint

Confirmed

Package_DIP/DIP-40_W15.24mm

Pad Layout

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

Pads (40)

Number	Type
1	thru hole
2	thru hole
3	thru hole
4	thru hole
5	thru hole
6	thru hole
7	thru hole
8	thru hole
9	thru hole
10	thru hole
11	thru hole
12	thru hole
13	thru hole
14	thru hole
15	thru hole
16	thru hole
17	thru hole
18	thru hole
19	thru hole
20	thru hole
21	thru hole
22	thru hole
23	thru hole
24	thru hole
25	thru hole
26	thru hole
27	thru hole
28	thru hole
29	thru hole
30	thru hole
31	thru hole
32	thru hole
33	thru hole
34	thru hole
35	thru hole
36	thru hole
37	thru hole
38	thru hole
39	thru hole
40	thru hole

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