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STC8G1K08A-36I-DFN8
Single Chip MCU based on the 8051 architecture, 8KiB Flash, 1.25KiB SRAM, 4KiB EEPROM, 1.9..5.5V, 36 MHz, 6 GPIO, DFN-8
Schematic Symbol
Pin Configuration (9 pins)
| Pin | Name | Type |
|---|---|---|
| 9 | EPAD | passive |
| 1 | P5.4 | bidirectional |
| 2 | VCC | power_in |
| 3 | P5.5 | bidirectional |
| 4 | GND | power_in |
| 5 | P3.0 | bidirectional |
| 6 | P3.1 | bidirectional |
| 7 | P3.2 | bidirectional |
| 8 | P3.3 | bidirectional |
Footprint
ConfirmedPackage_DFN_QFN/DFN-8-1EP_3x3mm_P0.5mm_EP1.7x2.4mm
Pad Layout
—
1
2
3
4
5
6
7
8
9
Pads (10)
| Number | Type |
|---|---|
| — | smd |
| 1 | smd |
| 2 | smd |
| 3 | smd |
| 4 | smd |
| 5 | smd |
| 6 | smd |
| 7 | smd |
| 8 | smd |
| 9 | smd |