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CY14V256LA-BA

256-Kbit (32K x 8-bit) nvSRAM, core VCC = 3.0V to 3.6V, I/O VCCQ = 1.65V to 1.95V, 35ns, TFBGA-48

Schematic Symbol

CY14V256LA-BAVCCVCCVSSVSS~{OE}A0A1A2A3A4~{CE}A5A6A7VCCQVCCQVCAPVSSA14VSSA12A13~{WE}A8A9A10A11NCNCNCNCDQ0NCDQ4DQ1NCDQ5DQ2DQ6DQ3NCNCDQ7NC~{HSB}NCNCNC

Pin Configuration (48 pins)

PinNameType
A6VCCpower_in
C2VCCpassive
D1VSSpower_in
E4VSSpassive
A1NCno_connect
A2~{OE}input
A3A0input
A4A1input
A5A2input
B1NCno_connect
B2NCno_connect
B3A3input
B4A4input
B5~{CE}input
B6NCno_connect
C1DQ0tri_state
C3A5input
C4A6input
C5NCno_connect
C6DQ4tri_state
D2DQ1tri_state
D3NCno_connect
D4A7input
D5DQ5tri_state
D6VCCQpower_in
E1VCCQpassive
E2DQ2tri_state
E3VCAPpower_in
E5DQ6tri_state
E6VSSpassive
F1DQ3tri_state
F2NCno_connect
F3A14input
F4VSSpassive
F5NCno_connect
F6DQ7tri_state
G1NCno_connect
G2~{HSB}bidirectional
G3A12input
G4A13input
G5~{WE}input
G6NCno_connect
H1NCno_connect
H2A8input
H3A9input
H4A10input
H5A11input
H6NCno_connect

Footprint

Confirmed

Package_BGA/Infineon_TFBGA-48_6x10mm_Layout6x8_P0.75mm

Pad Layout
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
G1
G2
G3
G4
G5
G6
H1
H2
H3
H4
H5
H6
Pads (48)
NumberType
A1smd
A2smd
A3smd
A4smd
A5smd
A6smd
B1smd
B2smd
B3smd
B4smd
B5smd
B6smd
C1smd
C2smd
C3smd
C4smd
C5smd
C6smd
D1smd
D2smd
D3smd
D4smd
D5smd
D6smd
E1smd
E2smd
E3smd
E4smd
E5smd
E6smd
F1smd
F2smd
F3smd
F4smd
F5smd
F6smd
G1smd
G2smd
G3smd
G4smd
G5smd
G6smd
H1smd
H2smd
H3smd
H4smd
H5smd
H6smd

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Footprint

Details

Pin Count48
FootprintInfineon_TFBGA-48_6x10mm_Layout6x8_P0.75mm
Pad Count48
View Datasheet