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MT48LC32M8A2TG

256M – (32M x 8 bit) Synchronous DRAM (SDRAM), TSOP-II-54

Schematic Symbol

MT48LC32M8A2TGVDDVDDQVSSQVDDQVSSQVDD~{WE}~{CAS}~{RAS}~{CS}BA0BA1A10A0A1A2A3VDDVSSA4A5A6A7A8A9A11A12CKECLKDQMVSSVDDQVSSQVDDQVSSQVSSDQ0NCDQ1NCDQ2NCDQ3NCNCNCNCDQ4NCDQ5NCDQ6NCDQ7

Pin Configuration (54 pins)

PinNameType
1VDDpower_in
2DQ0bidirectional
3VDDQpower_in
4NCno_connect
5DQ1bidirectional
6VSSQpower_in
7NCno_connect
8DQ2bidirectional
9VDDQpassive
10NCno_connect
11DQ3bidirectional
12VSSQpassive
13NCno_connect
14VDDpassive
15NCno_connect
16~{WE}input
17~{CAS}input
18~{RAS}input
19~{CS}input
20BA0input
21BA1input
22A10input
23A0input
24A1input
25A2input
26A3input
27VDDpassive
28VSSpower_in
29A4input
30A5input
31A6input
32A7input
33A8input
34A9input
35A11input
36A12input
37CKEinput
38CLKinput
39DQMinput
40NCno_connect
41VSSpassive
42NCno_connect
43VDDQpassive
44DQ4bidirectional
45NCno_connect
46VSSQpassive
47DQ5bidirectional
48NCno_connect
49VDDQpassive
50DQ6bidirectional
51NCno_connect
52VSSQpassive
53DQ7bidirectional
54VSSpassive

Footprint

Confirmed

Package_SO/TSOP-II-54_22.2x10.16mm_P0.8mm

Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pads (54)
NumberType
1smd
2smd
3smd
4smd
5smd
6smd
7smd
8smd
9smd
10smd
11smd
12smd
13smd
14smd
15smd
16smd
17smd
18smd
19smd
20smd
21smd
22smd
23smd
24smd
25smd
26smd
27smd
28smd
29smd
30smd
31smd
32smd
33smd
34smd
35smd
36smd
37smd
38smd
39smd
40smd
41smd
42smd
43smd
44smd
45smd
46smd
47smd
48smd
49smd
50smd
51smd
52smd
53smd
54smd

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Footprint

Details

LibraryMemory_RAM
Pin Count54
FootprintTSOP-II-54_22.2x10.16mm_P0.8mm
Pad Count54
View Datasheet