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TPD3E001DRLR
TPD3E001 Low-Capacitance 3-Channel ESD-Protection for High-Speed Data Interfaces
Schematic Symbol
Pin Configuration (5 pins)
| Pin | Name | Type |
|---|---|---|
| 1 | IO1 | passive |
| 2 | IO2 | passive |
| 3 | passive | |
| 4 | IO3 | passive |
| 5 | passive |
Footprint
ConfirmedPackage_TO_SOT_SMD/SOT-553
Pad Layout
1
2
3
4
5
Pads (5)
| Number | Type |
|---|---|
| 1 | smd |
| 2 | smd |
| 3 | smd |
| 4 | smd |
| 5 | smd |