Si5342A-D

Jitter Attenuator/Clock Multiplier, 2 channel, Fractional, 0.001-1028 MHz, QFN-44

Schematic Symbol

Pin Configuration (45 pins)

Pin	Name	Type
1	IN1	input
2	IN1b	input
3	IN_SEL0	input
4	X1	input
5	XA	input
6	XB	input
7	X2	input
8	VDDA	power_in
9	VDDA	passive
10	IN2	input
11	IN2b	input
12	~{OE}	input
13	SDA/SDIO	bidirectional
14	SCLK	input
15	A1/SDO	bidirectional
16	A0/~{CS}	input
17	~{RST}	input
18	VDDO0	power_in
19	OUT0b	output
20	OUT0	output
21	VDD	power_in
22	NC	no_connect
23	VDDO1	power_in
24	OUT1b	output
25	OUT1	output
26	VDDS	power_in
27	~{LOL}	output
28	~{LOS_XAXB}	output
29	VDDS	passive
30	~{LOS0}	output
31	~{LOS1}	output
32	VDD	passive
33	~{INTR}	output
34	VDDS	passive
35	~{LOS2}	output
36	~{LOS3}	output
37	IN_SEL1	input
38	I2C_SEL	input
39	VDD	passive
40	VDD	passive
41	IN3/FB_IN	input
42	IN3b/FB_INb	input
43	IN0	input
44	IN0b	input
45	GND	power_in

Footprint

Confirmed

Package_DFN_QFN/QFN-44-1EP_7x7mm_P0.5mm_EP5.2x5.2mm

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