Reference schematic

AcCCS

IdahoLabResearch-AcCCS-AcCCS-schematic

Loading the viewer…

IdahoLabResearch-AcCCS-AcCCS-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
106Placed parts
20Net labels
KiCad 7File format

Bill of materials

106 distinct parts

97 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
C1100nFDevice:C
C247nFDevice:C
C3100nFDevice:C
C4100nFDevice:C
D1~Device:D
D10~Device:D
D11~Device:D
D12LEDDevice:LED
D13LEDDevice:LED
D14LEDDevice:LED
D15LEDDevice:LED
D16LEDDevice:LED
D17ZPD10Device:D_Zener
D18ZPD12Device:D_Zener
D19ZPD10Device:D_Zener
D2~Device:D
D20ZPD10Device:D_Zener
D21ZPD5.1Device:D_Zener
D22ZPD10Device:D_Zener
D23ZPD10Device:D_Zener
D24ZPD12Device:D_Zener
D25ZPD10Device:D_Zener
D3LEDDevice:LED
D4LEDDevice:LED
D5LEDDevice:LED
D6~Device:D
D7~Device:D
D8~Device:D
D9~Device:D
J1GNDConnector:Screw_Terminal_01x04
J2+12VConnector:Screw_Terminal_01x04
J3-12VConnector:Screw_Terminal_01x04
J4+5VConnector:Screw_Terminal_01x04
J5GNDConnector:Screw_Terminal_01x04
J6PWM Test PointConnector:Conn_01x01_Pin
J7OUTPUTSConnector:Screw_Terminal_01x04
J8I2CConnector:Conn_01x02_Pin
K1SRD-05VDC-SL-CRelay:SANYOU_SRD_Form_C
K2SRD-05VDC-SL-CRelay:SANYOU_SRD_Form_C
K3SRD-05VDC-SL-CRelay:SANYOU_SRD_Form_C
Show the other 66
K4SRD-05VDC-SL-CRelay:SANYOU_SRD_Form_C
K5SRD-05VDC-SL-CRelay:SANYOU_SRD_Form_C
Q12SC1815Transistor_BJT:2SC1815
Q10G75P04TDevice:Q_PMOS_GDS
Q11G75P04TDevice:Q_PMOS_GDS
Q12G75P04TDevice:Q_PMOS_GDS
Q13G75P04TDevice:Q_PMOS_GDS
Q14G75P04TDevice:Q_PMOS_GDS
Q22SC1815Transistor_BJT:2SC1815
Q32SC1815Transistor_BJT:2SC1815
Q42SC1815Transistor_BJT:2SC1815
Q52SC1815Transistor_BJT:2SC1815
Q6GT088N06TDevice:Q_NMOS_GDS
Q7GT088N06TDevice:Q_NMOS_GDS
Q8GT088N06TDevice:Q_NMOS_GDS
Q9G75P04TDevice:Q_PMOS_GDS
R124kDevice:R
R102.2kDevice:R
R11470Device:R
R122.2kDevice:R
R13100Device:R
R141kDevice:R
R152.2kDevice:R
R16330Device:R
R17150Device:R
R18470Device:R
R19330Device:R
R24.7kDevice:R
R20510Device:R
R212.2kDevice:R
R22510Device:R
R23510Device:R
R24510Device:R
R25510Device:R
R26510Device:R
R271kDevice:R
R281kDevice:R
R291kDevice:R
R3680Device:R
R301kDevice:R
R311kDevice:R
R32100kDevice:R
R33100kDevice:R
R34100kDevice:R
R35100kDevice:R
R36100kDevice:R
R37100kDevice:R
R38100kDevice:R
R39100kDevice:R
R41kDevice:R
R40100kDevice:R
R51kDevice:R
R64.7kDevice:R
R710kDevice:R
R847kDevice:R
R9680Device:R
RV12k PotDevice:R_Potentiometer
RV22k PotDevice:R_Potentiometer
U1TLC555CPTimer:TLC555xP
U2LM6132BIN/NOPBSimulation_SPICE:OPAMP
U3MCP23008-xPInterface_Expansion:MCP23008-xP
U4SFH617A-1Isolator:SFH617A-1
U5SFH617A-1Isolator:SFH617A-1
U6SFH617A-1Isolator:SFH617A-1
U7SFH617A-1Isolator:SFH617A-1
U8SFH617A-1Isolator:SFH617A-1

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.