Reference schematic

Bondwell1MB

clarking-Bondwell1MB-Bondwell1MB-schematic

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clarking-Bondwell1MB-Bondwell1MB-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
38Placed parts
39Net labels
KiCad 6File format

Bill of materials

38 distinct parts

29 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
C10.1uFDevice:C_Small
C1022uF 16vDevice:CP1
C20.1uFDevice:C_Small
C30.1uFDevice:C_Small
C40.1uFDevice:C_Small
C50.1uFDevice:C_Small
C60.1uFDevice:C_Small
C70.1uFDevice:C_Small
C80.1uFDevice:C_Small
C90.1uFDevice:C_Small
J1Conn_01x05Connector_Generic:Conn_01x05
J5Conn_01x18Connector_Generic:Conn_01x18
J6Conn_01x18Connector_Generic:Conn_01x18
JA9SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JC0SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JC1SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JC2SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JC3SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JOE1SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JP10SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP11SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP12SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP13SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP14SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP15SolderJumper_2_OpenJumper:SolderJumper_2_Open
JP9SolderJumper_2_OpenJumper:SolderJumper_2_Open
JR0SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
JR1SolderJumper_2_BridgedJumper:SolderJumper_2_Bridged
RN110kDevice:R_Network05_US
U1LH604256K-80ACustomChips:604256
U2LH604256K-80ACustomChips:604256
U3LH604256K-80ACustomChips:604256
U4LH604256K-80ACustomChips:604256
U5GAL16V8Logic_Programmable:GAL16V8
U6LH604256K-80ACustomChips:604256
U7LH604256K-80ACustomChips:604256
U8LH604256K-80ACustomChips:604256
U9LH604256K-80ACustomChips:604256

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.