Reference schematic

Nixie Clock for Dalibor Farny Tubes

davidmcq137-NixiePCB-2-NixiePCB-schematic

Loading the viewer…

davidmcq137-NixiePCB-2-NixiePCB-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
75Placed parts
12Net labels
KiCad 7File format

Bill of materials

75 distinct parts

33 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
C1CP1NixieClockV1-rescue:CP1-Device
C2CP1NixieClockV1-rescue:CP1-Device
J1To/From ProcessorNixieClockV1-rescue:Conn_01x06_Male-Connector
J2Q5NixieClockV1-rescue:Conn_01x01_Male-Connector
J3Q6NixieClockV1-rescue:Conn_01x01_Male-Connector
J4Q7NixieClockV1-rescue:Conn_01x01_Male-Connector
J5Q8NixieClockV1-rescue:Conn_01x01_Male-Connector
J612V inputNixieClockV1-rescue:Conn_01x02_Male-Connector
J7170V InNixieClockV1-rescue:Conn_01x02_Male-Connector
N1R|Z568Mmedido:R|Z568M
N2R|Z568Mmedido:R|Z568M
N3Separatormedido:Separator
N4R|Z568Mmedido:R|Z568M
N5R|Z568Mmedido:R|Z568M
N6Separatormedido:Separator
N7R|Z568Mmedido:R|Z568M
N8R|Z568Mmedido:R|Z568M
Q1MPSA42Device:Q_NPN_EBC
Q2MPSA42Device:Q_NPN_EBC
Q3MPSA42Device:Q_NPN_EBC
Q4MPSA42Device:Q_NPN_EBC
R13K3Device:R_Small_US
R103K3Device:R_Small_US
R118K2Device:R_Small_US
R123K3Device:R_Small_US
R138K2Device:R_Small_US
R143K3Device:R_Small_US
R156K8Device:R_Small_US
R166K8Device:R_Small_US
R1768KDevice:R_Small_US
R1868KDevice:R_Small_US
R193K3Device:R_Small_US
R28K2Device:R_Small_US
R208K2Device:R_Small_US
R213K3Device:R_Small_US
R228K2Device:R_Small_US
R231Device:R_Small_US
R24R_Small_USDevice:R_Small_US
R25R_Small_USDevice:R_Small_US
R26R_Small_USDevice:R_Small_US
Show the other 35
R27R_Small_USDevice:R_Small_US
R28R_Small_USDevice:R_Small_US
R29R_Small_USDevice:R_Small_US
R33K3Device:R_Small_US
R30R_Small_USDevice:R_Small_US
R31R_Small_USDevice:R_Small_US
R32R_Small_USDevice:R_Small_US
R48K2Device:R_Small_US
R53K3Device:R_Small_US
R66K8Device:R_Small_US
R76K8Device:R_Small_US
R868KDevice:R_Small_US
R968KDevice:R_Small_US
U1FOD832medido:FOD832
U1074HC4094medido:74HC4094
U11FOD832medido:FOD832
U1274141NixieClockV1-rescue:74141-74xx_IEEE
U13FOD832medido:FOD832
U14FOD832medido:FOD832
U1574141NixieClockV1-rescue:74141-74xx_IEEE
U1674HC4094medido:74HC4094
U177805Regulator_Linear:LM7805_TO220
U18FOD832medido:FOD832
U1974141NixieClockV1-rescue:74141-74xx_IEEE
U274141NixieClockV1-rescue:74141-74xx_IEEE
U2074HC4094medido:74HC4094
U21medido2_Particle_Photon2NixiePhoton2Ctrl-rescue:Particle_Photon2-medido2
U22medido2_DS3231RTCNixiePhoton2Ctrl-rescue:DS3231RTC-medido2
U374HC4094medido:74HC4094
U4FOD832medido:FOD832
U574141NixieClockV1-rescue:74141-74xx_IEEE
U6FOD832medido:FOD832
U7FOD832medido:FOD832
U874141NixieClockV1-rescue:74141-74xx_IEEE
U974HC4094medido:74HC4094

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.