Reference schematic

RENEGADE

frederic-mahe-jtcores-jtcores-schematic

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frederic-mahe-jtcores-jtcores-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
17Placed parts
55Net labels
KiCad 6File format

Bill of materials

15 distinct parts

12 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
EE1174LS138jt74:74LS138
EE1374LS139jt74:74LS139
FF1127256Memory_EPROM:27256
FF1327256Memory_EPROM:27256
FF1427256Memory_EPROM:27256
FF427256Memory_EPROM:27256
FF627256Memory_EPROM:27256
FF827256Memory_EPROM:27256
GG174LS86jt74:74LS86
GG1127256Memory_EPROM:27256
GG1327256Memory_EPROM:27256
GG1427256Memory_EPROM:27256
GG427256Memory_EPROM:27256
GG627256Memory_EPROM:27256
GG827256Memory_EPROM:27256

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.