Reference layout
Intex Swg Pcb
jingsno-intex-swg-pcb-intex-swg-pcb-layout
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jingsno-intex-swg-pcb-intex-swg-pcb-layout
The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).
14Placed parts
46Nets
2Copper layers
70 × 90 mmBoard size
yesRouted
KiCad 5File format
Bill of materials
11 distinct parts
8 resolve to something in the catalog — click through to the footprint.
| Ref | Value | Footprint | Qty |
|---|---|---|---|
| B1 | Sparkfun BOB-12009 | Boards:SPARKFUN_LOGIC_LEVEL_CONVERTER | |
| F1 | 3A/250V | Fuse:Fuse_Littelfuse-LVR100 | |
| J1 | 230V | TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-2_1x02_P5.00mm_Horizontal | |
| J2 | Relay Board | TerminalBlock_Phoenix:TerminalBlock_Phoenix_MKDS-1,5-3_1x03_P5.00mm_Horizontal | |
| J3 | Display Board | Connector_JST:JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical | |
| J4 | Main Board | Connector_JST:JST_XH_B4B-XH-A_1x04_P2.50mm_Vertical | |
| J5 | 5V_INTEX Pin Select | Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical | |
| J6 | GND Pin Select | Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical | |
| MD1 | ESP32-DevKitC | Espressif_ESP32-DevKitC:Espressif-ESP32-DevKitC_V4-0-0-MFG | |
| PS1 | HLK-PM03 | Converter_ACDC:Converter_ACDC_HiLink_HLK-PMxx | |
| REF** | MountingHole_3.2mm_M3 | MountingHole:MountingHole_3.2mm_M3 |
Provenance
- Repository
- jingsno/intex-swg-pcb ↗
- Commit
- unknown
- Licence
- CC-BY-4.0
How it is used
Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.