Reference layout

Solar DataAcq EnvironmentBoard

lhr-solar-DataAcq-EnvironmentBoard-DataAcq-EnvironmentBoard-layout

Loading the viewer…

lhr-solar-DataAcq-EnvironmentBoard-DataAcq-EnvironmentBoard-layout

The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).

33Placed parts
36Nets
2Copper layers
53.95 × 58.99 mmBoard size
yesRouted
KiCad 8File format

Bill of materials

33 distinct parts

21 resolve to something in the catalog — click through to the footprint.

RefValueFootprintQty
C10.1uFCapacitor_SMD:C_0805_2012Metric
C20.1uFCapacitor_SMD:C_0805_2012Metric
C30.1uFCapacitor_SMD:C_0805_2012Metric
C41uFCapacitor_SMD:C_0805_2012Metric
C50.1uFCapacitor_SMD:C_0805_2012Metric
C60.1uFCapacitor_SMD:C_0805_2012Metric
C71uFCapacitor_SMD:C_0805_2012Metric
D112VLED_SMD:LED_0805_2012Metric
D23.3VLED_SMD:LED_0805_2012Metric
D3ESD9BDiode_SMD:D_SOD-923
D4ESD9BDiode_SMD:D_SOD-923
D5ESD9BDiode_SMD:D_SOD-923
D6ESD9BDiode_SMD:D_SOD-923
F1250mAFuse:Fuse_0603_1608Metric
F2250mAFuse:Fuse_0603_1608Metric
J2CAN OutputUTSVT_Connectors:Molex_MicroFit3.0_1x4xP3.00mm_PolarizingPeg_Vertical
J3CAN InputUTSVT_Connectors:Molex_MicroFit3.0_1x4xP3.00mm_PolarizingPeg_Vertical
J6Breakout ConnectorConnector_Molex:Molex_Nano-Fit_105310-xx10_2x05_P2.50mm_Vertical
LOGO1Arrowimages:arrow
LOGO2Dr. HallockUTSVT_Special:Hallock_Image_Tiny
LOGO3UTSVT LogoUTSVT_Special:UTSVT_Logo_Symbol
LOGO4Wolfimages:wolf
R11kResistor_SMD:R_0805_2012Metric
R222.1kResistor_SMD:R_0805_2012Metric
R32.2kResistor_SMD:R_0805_2012Metric
TP1TestPointUTSVT_Special:TestPoint_HEX_3mmID
TP2TestPointUTSVT_Special:TestPoint_HEX_3mmID
TP4TestPointUTSVT_Special:TestPoint_HEX_3mmID
TP5TestPointUTSVT_Special:TestPoint_HEX_3mmID
U1SHT45Sensor_Humidity:Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad
U2FS3000-1005SamacSys_Parts:FS30001005
U3LMT87DCKPackage_TO_SOT_SMD:SOT-353_SC-70-5
U4Daughterboard ConnectorUTSVT_Special:PeripheralSOM

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.