Reference layout
PCI-Express x8 Breakout
mwrnd-PCIe_x8_Breakout-PCIe_x8_Breakout-layout
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mwrnd-PCIe_x8_Breakout-PCIe_x8_Breakout-layout
The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).
42Placed parts
56Nets
4Copper layers
39.3 × 51.3 mmBoard size
yesRouted
KiCad 7File format
Bill of materials
42 distinct parts
8 resolve to something in the catalog — click through to the footprint.
| Ref | Value | Footprint | Qty |
|---|---|---|---|
| J1 | PCI_Express_x8 | Connector_PCBEdge:BUS_PCIexpress_x8 | |
| J10 | Rx3_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J11 | Rx4_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J12 | Rx4_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J13 | Rx5_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J14 | Rx5_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J15 | Rx6_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J16 | Rx6_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J17 | Rx7_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J18 | Rx7_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J19 | Tx0_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J2 | Rx1_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J20 | Tx0_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J21 | Tx1_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J22 | Tx1_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J23 | Tx2_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J24 | Tx2_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J25 | Tx3_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J26 | Tx3_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J27 | Tx4_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J28 | Tx4_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J29 | Tx5_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J3 | Rx0_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J30 | Tx5_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J31 | Tx6_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J32 | Tx6_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J33 | Tx7_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J34 | Tx7_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J35 | CLK_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J36 | CLK_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J4 | Rx0_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J5 | Rx1_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J6 | Rx2_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J7 | Conn_02x08_Odd_Even | Connector_PinSocket_2.54mm:PinSocket_2x08_P2.54mm_Vertical | |
| J8 | Rx2_N | U.FL_w_Label:U.FL_Hirose_w_Label | |
| J9 | Rx3_P | U.FL_w_Label:U.FL_Hirose_w_Label | |
| R1 | DNP | Resistor_SMD:R_0603_1608Metric | |
| TP1 | GND | Connector_PinSocket_2.54mm:PinSocket_1x01_P2.54mm_Vertical | |
| TP6 | PRSNT1 | Connector_PinHeader_1.00mm:PinHeader_1x01_P1.00mm_Vertical | |
| TP7 | PRSNT2_x1 | Connector_PinHeader_1.00mm:PinHeader_1x01_P1.00mm_Vertical |
Show the other 2
| TP8 | PRSNT2_x4 | Connector_PinHeader_1.00mm:PinHeader_1x01_P1.00mm_Vertical | |
| TP9 | PRSNT2_x8 | Connector_PinHeader_1.00mm:PinHeader_1x01_P1.00mm_Vertical |
Provenance
- Repository
- mwrnd/PCIe_x8_Breakout ↗
- Commit
- 260c36b70c917e3db7f27fdc6705482f9273e062
- Licence
- BSD-2-Clause
How it is used
Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.