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Reference layout

Electronics BOARD17

orri93-electronics-board17-electronics-layout

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orri93-electronics-board17-electronics-layout

The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).

33Placed parts
18Nets
2Copper layers
58.67 × 47.75 mmBoard size
yesRouted
KiCad 8File format

Bill of materials

33 distinct parts

33 resolve to something in the catalog — click through to the footprint.

RefValueFootprintQty
C12.2uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
C22.2uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
C347uFCapacitor_SMD:CP_Elec_6.3x7.7
C42.2uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
C52.2uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
C62.2uFCapacitor_SMD:CP_Elec_4x5.4
C72.2uFCapacitor_SMD:CP_Elec_4x5.4
C80.1uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
C90.1uFCapacitor_SMD:C_1206_3216Metric_Pad1.33x1.80mm_HandSolder
D11N4148Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal
D21N4148Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal
J15VConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J2GNDConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J3+VDCConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J4GND VDCConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J5-VDCConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J6OutputConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
J7GND OutputConnector_Pin:Pin_D1.1mm_L8.5mm_W2.5mm_FlatFork
MK1~Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical
Q1BC547Package_TO_SOT_THT:TO-92_Inline
R110kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R2100kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R33.3kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R410kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R51MResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R610kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
R710kResistor_SMD:R_1206_3216Metric_Pad1.30x1.75mm_HandSolder
TP1MK Power GNDTestPoint:TestPoint_Loop_D2.50mm_Drill1.0mm
TP2MK PowerTestPoint:TestPoint_Loop_D2.50mm_Drill1.0mm
TP3MK -TestPoint:TestPoint_Loop_D2.50mm_Drill1.0mm
TP4MK +TestPoint:TestPoint_Loop_D2.50mm_Drill1.0mm
TP5Q OutputTestPoint:TestPoint_Loop_D2.50mm_Drill1.0mm
U1CA3140Package_SO:SOIC-8_3.9x4.9mm_P1.27mm

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.