Reference schematic
Restall MsfOwlClock
pete-restall-MsfOwlClock-10-MsfOwlClock-schematic
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pete-restall-MsfOwlClock-10-MsfOwlClock-schematic
Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).
Bill of materials
28 distinct parts
7 resolve to something in the catalog — click through to the component.
| Ref | Value | Symbol | Qty |
|---|---|---|---|
| C1 | ${SIM.PARAMS} | restall-generic-capacitors:capacitor-unpolarised | |
| C2 | ${SIM.PARAMS} | restall-generic-capacitors:capacitor-unpolarised | |
| C3 | ${SIM.PARAMS} | restall-generic-capacitors:capacitor-unpolarised | |
| Camp1 | ${SIM.PARAMS} | restall-generic-capacitors:capacitor-unpolarised | |
| Cbypass1 | 22u | restall-generic-capacitors:capacitor-unpolarised | |
| Cbypass2 | 22u | restall-generic-capacitors:capacitor-unpolarised | |
| Cbypass3 | 4.7u | restall-generic-capacitors:capacitor-unpolarised | |
| Cbypass4 | 4.7u | restall-generic-capacitors:capacitor-unpolarised | |
| Cdac1 | ${SIM.PARAMS} | restall-generic-capacitors:capacitor-unpolarised | |
| Cref1 | 4.7u | restall-generic-capacitors:capacitor-unpolarised | |
| FB1 | WLBD2012HCU121TH | restall-generic-inductors:ferrite-bead | |
| R1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| R2 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| R3 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| R4 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Ramp1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Rdac1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Rref1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Rref2 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Rsim_1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| Rspk1 | ${SIM.PARAMS} | restall-generic-resistors:resistor | |
| U1 | MCP6486 | Simulation_SPICE:OPAMP | |
| V1 | 5 | Simulation_SPICE:VDC | |
| V2 | VSIN | Simulation_SPICE:VSIN | |
| Vamp1 | 2.5 | Simulation_SPICE:VDC | |
| Vamp2 | ${SIM.PARAMS} | Simulation_SPICE:VDC | |
| Vamp3 | ${SIM.PARAMS} | Simulation_SPICE:VDC | |
| Vspk1 | ${SIM.PARAMS} | Simulation_SPICE:VDC |
Provenance
- Repository
- pete-restall/MsfOwlClock ↗
- Commit
- unknown
- Licence
- CC-BY-4.0
How it is used
Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.