Reference layout
TTL Clock
skiselev-ttl-clock-ttl-clock-layout
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skiselev-ttl-clock-ttl-clock-layout
The project archive carries the board, its project file and the upstream licence. The archive is zstd-compressed (tar.zst).
64Placed parts
162Nets
2Copper layers
100 × 100 mmBoard size
yesRouted
KiCad 5File format
Bill of materials
64 distinct parts
12 resolve to something in the catalog — click through to the footprint.
| Ref | Value | Footprint | Qty |
|---|---|---|---|
| C1 | 100nF | My_Components:Cap_Cer_762 | |
| C10 | 100nF | My_Components:Cap_Cer_762 | |
| C11 | 100nF | My_Components:Cap_Cer_762 | |
| C12 | 100nF | My_Components:Cap_Cer_762 | |
| C13 | 100nF | My_Components:Cap_Cer_762 | |
| C14 | 100nF | My_Components:Cap_Cer_762 | |
| C15 | 100nF | My_Components:Cap_Cer_762 | |
| C16 | 100nF | My_Components:Cap_Cer_762 | |
| C17 | 100uF | Capacitor_THT:CP_Radial_D6.3mm_P2.50mm | |
| C18 | 12pF | My_Components:Cap_Cer_508 | |
| C19 | 5-30pF | My_Components:C_Trim_Murata | |
| C2 | 100nF | My_Components:Cap_Cer_762 | |
| C3 | 100nF | My_Components:Cap_Cer_762 | |
| C4 | 100nF | My_Components:Cap_Cer_762 | |
| C5 | 100nF | My_Components:Cap_Cer_762 | |
| C6 | 100nF | My_Components:Cap_Cer_762 | |
| C7 | 100nF | My_Components:Cap_Cer_762 | |
| C8 | 100nF | My_Components:Cap_Cer_762 | |
| C9 | 100nF | My_Components:Cap_Cer_762 | |
| D1 | LED | LED_THT:LED_D3.0mm_FlatTop | |
| D2 | LED | LED_THT:LED_D3.0mm_FlatTop | |
| D3 | LED | LED_THT:LED_D3.0mm_FlatTop | |
| D4 | LED | LED_THT:LED_D3.0mm_FlatTop | |
| HOLE1 | CONN_1 | MountingHole:MountingHole_3mm_Pad_Via | |
| HOLE2 | CONN_1 | MountingHole:MountingHole_3mm_Pad_Via | |
| HOLE3 | CONN_1 | MountingHole:MountingHole_3mm_Pad_Via | |
| HOLE4 | CONN_1 | MountingHole:MountingHole_3mm_Pad_Via | |
| P1 | 5V | My_Components:Conn_Power_Jack_Circular_Pads | |
| R1 | 4.7k | My_Components:Res_762 | |
| R2 | 4.7k | My_Components:Res_762 | |
| R3 | 4.7k | My_Components:Res_762 | |
| R4 | 4.7k | My_Components:Res_762 | |
| R5 | 4.7k | My_Components:Res_762 | |
| R6 | 330k | My_Components:Res_762 | |
| R7 | 15M | My_Components:Res_762 | |
| RP1 | 470 | My_Components:IC_DIP16_300 | |
| RP2 | 470 | My_Components:IC_DIP16_300 | |
| RP3 | 470 | My_Components:IC_DIP16_300 | |
| RP4 | 470 | My_Components:IC_DIP16_300 | |
| RP5 | 470 | My_Components:IC_DIP16_300 |
Show the other 24
| RP6 | 470 | My_Components:IC_DIP16_300 | |
| SW1 | SECONDS | My_Components:Switch_SPDP_D2F | |
| SW2 | MINUTES | My_Components:Switch_SPDP_D2F | |
| SW3 | HOURS | My_Components:Switch_SPDP_D2F | |
| U1 | 74HCT4060 | My_Components:IC_DIP16_300 | |
| U10 | 74LS47 | My_Components:IC_DIP16_300 | |
| U11 | 74LS90 | My_Components:IC_DIP14_300 | |
| U12 | 74LS90 | My_Components:IC_DIP14_300 | |
| U13 | 74LS90 | My_Components:IC_DIP14_300 | |
| U14 | 74LS90 | My_Components:IC_DIP14_300 | |
| U15 | 74LS90 | My_Components:IC_DIP14_300 | |
| U16 | 74LS90 | My_Components:IC_DIP14_300 | |
| U17 | DA56-11SRWA | Display_7Segment:DA56-11SURKWA | |
| U18 | DA56-11SRWA | Display_7Segment:DA56-11SURKWA | |
| U19 | DA56-11SRWA | Display_7Segment:DA56-11SURKWA | |
| U2 | 74LS00 | My_Components:IC_DIP14_300 | |
| U3 | 74LS00 | My_Components:IC_DIP14_300 | |
| U4 | 74LS00 | My_Components:IC_DIP14_300 | |
| U5 | 74LS47 | My_Components:IC_DIP16_300 | |
| U6 | 74LS47 | My_Components:IC_DIP16_300 | |
| U7 | 74LS47 | My_Components:IC_DIP16_300 | |
| U8 | 74LS47 | My_Components:IC_DIP16_300 | |
| U9 | 74LS47 | My_Components:IC_DIP16_300 | |
| Y1 | 32768Hz | My_Components:Crystal_32K_Horiz |
Provenance
- Repository
- skiselev/ttl-clock ↗
- Commit
- unknown
- Licence
- CC-BY-4.0
How it is used
Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.