Reference schematic

Block: Front Panel Board

storskegg-Block-amp-front-Block-amp-front-schematic

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storskegg-Block-amp-front-Block-amp-front-schematic

Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).

1Sheets
71Placed parts
2Net labels
KiCad 9File format

Bill of materials

71 distinct parts

71 resolve to something in the catalog — click through to the component.

RefValueSymbolQty
C168pFDevice:C
C101000nFDevice:C
C2CDevice:C
C3CDevice:C
C4CDevice:C
C5100nFDevice:C
C6100nFDevice:C
C7100nFDevice:C
C8100nFDevice:C
C91000nFDevice:C
D1LEDDevice:LED
D2LEDDevice:LED
D3LEDDevice:LED
D4LEDDevice:LED
H1MountingHoleMechanical:MountingHole
H2MountingHoleMechanical:MountingHole
H4MountingHoleMechanical:MountingHole
H5MountingHoleMechanical:MountingHole
H6MountingHoleMechanical:MountingHole
H7MountingHoleMechanical:MountingHole
H8MountingHoleMechanical:MountingHole
J1Pwr GND InConnector:Screw_Terminal_01x01
J10Pwr +30V OutConnector:Screw_Terminal_01x01
J11Pwr +30V OutConnector:Screw_Terminal_01x01
J12Pwr +30V OutConnector:Screw_Terminal_01x01
J13Sig_to_Stg1Connector:Screw_Terminal_01x01
J14Sig_in_phonoConnector:Screw_Terminal_01x01
J16Gnd_in_phonoConnector:Screw_Terminal_01x01
J17Stg2_pent_gndConnector:Screw_Terminal_01x01
J18Stg2_pent_S2Connector:Screw_Terminal_01x01
J19Stg2_pent_pwrConnector:Screw_Terminal_01x01
J2Pwr +9V InConnector:Screw_Terminal_01x01
J20Sig_de_Stg2Connector:Screw_Terminal_01x01
J21Sig_to_Stg3Connector:Screw_Terminal_01x01
J22sig_gndConnector:Screw_Terminal_01x01
J26Bal_Vol_gndConnector:Screw_Terminal_01x01
J27Bal_vol_to_xformrConnector:Screw_Terminal_01x01
J28Vol_gndConnector:Screw_Terminal_01x01
J29Unbal_Vol_gndConnector:Screw_Terminal_01x01
J3Pwr +30V InConnector:Screw_Terminal_01x01
Show the other 31
J30Unbal_vol_to_xformrConnector:Screw_Terminal_01x01
J32Sig_from_Stg3Connector:Screw_Terminal_01x01
J4Pwr GND OutConnector:Screw_Terminal_01x01
J5Pwr GND OutConnector:Screw_Terminal_01x01
J6Pwr GND OutConnector:Screw_Terminal_01x01
J7Pwr +9V OutConnector:Screw_Terminal_01x01
J8Pwr +9V OutConnector:Screw_Terminal_01x01
J9Pwr +9V OutConnector:Screw_Terminal_01x01
Q1LSK170Transistor_FET:2N3819
Q2LSK170Transistor_FET:2N3819
R11MDevice:R
R104MDevice:R_US
R114MDevice:R_US
R125.1kDevice:R_US
R135.1kDevice:R_US
R14100RDevice:R_US
R15100RDevice:R_US
R2100RDevice:R
R347kDevice:R
R4RDevice:R
R6360RDevice:R
R7360RDevice:R
R84MDevice:R_US
R94MDevice:R_US
RV1B1MDevice:R_Potentiometer
RV2B250kDevice:R_Potentiometer
RV3B250kDevice:R_Potentiometer
RV4B20kDevice:R_Potentiometer
RV5A1MDevice:R_Potentiometer
RV7B100kDevice:R_Potentiometer
RV8B100kDevice:R_Potentiometer

Provenance

Commit
unknown
Licence
CC-BY-4.0

How it is used

Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.