Reference schematic
FPGA IO board
zhiyb-fpga-7-fpga-schematic
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zhiyb-fpga-7-fpga-schematic
Take the project archive: a schematic is a root sheet plus every sub-sheet beside it, and the root alone opens with its hierarchy missing. The archive is zstd-compressed (tar.zst).
1Sheets
32Placed parts
39Net labels
KiCad 8File format
Bill of materials
32 distinct parts
32 resolve to something in the catalog — click through to the component.
| Ref | Value | Symbol | Qty |
|---|---|---|---|
| C1 | 100n | Device:C | |
| D1 | LED_RKGB | Device:LED_RKGB | |
| D2 | LED_RKGB | Device:LED_RKGB | |
| D3 | LED_RKGB | Device:LED_RKGB | |
| D4 | LED_RKGB | Device:LED_RKGB | |
| D5 | LED_RKGB | Device:LED_RKGB | |
| J1 | Conn_02x04_Odd_Even | Connector_Generic:Conn_02x04_Odd_Even | |
| J2 | Conn_02x20_Odd_Even | Connector_Generic:Conn_02x20_Odd_Even | |
| R1 | 330 | Device:R | |
| R10 | 330 | Device:R | |
| R11 | 330 | Device:R | |
| R12 | 330 | Device:R | |
| R13 | 330 | Device:R | |
| R14 | 330 | Device:R | |
| R15 | 330 | Device:R | |
| R2 | 330 | Device:R | |
| R3 | 330 | Device:R | |
| R4 | 330 | Device:R | |
| R5 | 330 | Device:R | |
| R6 | 330 | Device:R | |
| R7 | 330 | Device:R | |
| R8 | 330 | Device:R | |
| R9 | 330 | Device:R | |
| SW1 | SW_Push | Switch:SW_Push | |
| SW2 | SW_Push | Switch:SW_Push | |
| SW3 | SW_Push | Switch:SW_Push | |
| SW4 | SW_Push | Switch:SW_Push | |
| SW5 | SW_Push | Switch:SW_Push | |
| SW6 | SW_Push | Switch:SW_Push | |
| SW7 | SW_Push | Switch:SW_Push | |
| SW8 | SW_Push | Switch:SW_Push | |
| U1 | W25Q128JVS | Memory_Flash:W25Q128JVS |
Provenance
- Repository
- zhiyb/fpga ↗
- Commit
- unknown
- Licence
- CC-BY-4.0
How it is used
Trace's agent reads this design as context — what parts a board like this carries, how they are grouped across sheets, what a plausible layer stack and board size look like for the job. It is not copied. The licence above is permissive, and it, the repository and the commit are recorded so the origin of anything derived from it is always answerable.