SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.95x4.9mm_Mask2.71x3.4mm
Package_SO
SOIC, 8 Pin (JEDEC MS-012 variation BA (thermally enhanced), using tolerances and Exposed Pad from Texas Instruments DDA0008B, https://www.ti.com/lit/ml/pptd058j/pptd058j.pdf, https://www.ti.com/lit/ds/symlink/lm5017.pdf#page=35, https://www.jedec.org/document_search?search_api_views_fulltext=MS-012)
Footprint
9 pads
- Mount
- Surface mount
- Courtyard
- 7.4 × 5.4 mm
- Pads
- 9
- File
- 6 KB
3D model
noneno 3D model
This footprint names no 3D model, or names one the upstream package set never shipped. Nothing is shown rather than a model that 404s.
On real boards
The largest boards that carry it
| Design | Parts | Nets | Layers | Board | Licence | Source |
|---|---|---|---|---|---|---|
| MAINBOARD2 | 178 | 245 | 2 | 80 × 145 mm | CC-BY-4.0 | midarubiccube/mainboard2 ↗ |
| Magdy0 Proto V0 BOARD2 | 149 | 71 | 2 | 99.97 × 99.4 mm | CC-BY-4.0 | Omar-Magdy0/Proto_V0 ↗ |
| TGT Kicad Data ぱわこ | 106 | 85 | 4 | 100 × 50 mm | MIT | sabanekko3/TGT_kicad_data ↗ |
| 2425 Projet2A AresCFR BOARD5 | 35 | 59 | 2 | 38.75 × 40.16 mm | CC-BY-4.0 | AresEnsea/2425_Projet2A_AresCFR ↗ |
Provenance
- Source
- kicad-footprints
- Credit
- KiCad Libraries Contributors
- Licence
- CC-BY-SA-4.0-with-KiCad-exception