PEEL22CV10AP

Logic_Programmable

Not in Production, CMOS Programmable Electrically Erasable Logic Device, DIP-24

Symbol

24 pins
Schematic symbol for PEEL22CV10AP
Units
1
Kind
part
Grid
on 1.27 mm

Footprint

24 pads
Footprint for PEEL22CV10AP
Library
Package_DIP
Mount
through_hole
Courtyard
9.73 × 30.98 mm
Link
exact
Footprint page
Open →

3D model

STEP

Package_DIP_DIP-24_W7.62mm

7.87 × 31.75 × 6.98 mm

740 KB STEP

Library
Package_DIP_DIP-24
Link
exact
Model page
Open →

Pins and pads

Every pin on the symbol has a pad on the footprint.

PinNameTypePad
1I1/CLKinput1
2I2input2
3I3input3
4I4input4
5I5input5
6I6input6
7I7input7
8I8input8
9I9input9
10I10input10
11I11input11
12GNDpower_in12
13I13input13
14IO14tri_state14
15IO15tri_state15
16IO16tri_state16
17IO17tri_state17
18IO18tri_state18
19IO19tri_state19
20IO20tri_state20
21IO21tri_state21
22IO22tri_state22
23IO23tri_state23
24VCCpower_in24

On real boards

20+ designs use this part

1 placed it by name in a schematic; 19 carry its footprint on a board, and no other part in the catalog uses that footprint. Largest first.

Provenance

Credit
KiCad Libraries Contributors
Licence
CC-BY-SA-4.0-with-KiCad-exception
Link method
exact
Cross-check
passed